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data sheet, rev. 2 october 2001 fw323 05 1394a pci phy/link open host controller interface features n 1394a-2000 ohci link and phy core function in sin- gle device: enables smaller, simpler, more efficient mother- board and add-in card designs by replacing two components with one enables lower system costs leverages proven 1394a-2000 phy core design demonstrated compatibility with current microsoft windows ? drivers and common applications demonstrated interoperability with existing, as well as older, 1394 consumer electronics and periph- erals products feature-rich implementation for high performance in common applications supports low-power system designs (cmos implementation, power management features) provides lps, lkon, and cna outputs to support legacy power management implementations n ohci: complies with ohci 1.1 whql requirements complies with microsoft windows logo program system and device requirements listedon windows hardware compatibility list http://www.microsoft.com/hcl/results.asp compatible with microsoft windows and macos ? operating systems 4 kbyte isochronous transmit fifo 2 kbyte asynchronous transmit fifo 4 kbyte isochronous receive fifo 2 kbyte asychronous receive fifo dedicated asynchronous and isochronous descriptor-based dma engines eight isochronous transmit contexts eight isochronous receive contexts prefetches isochronous transmit data supports posted write transactions n 1394a-2000 phy core: compliant with ieee ? 1394a-2000, standard for a high performance serial bus (supplement) provides three fully compliant cable ports, each supporting 400 mbits/s, 200 mbits/s, and 100 mbits/s traffic supports extended bias_handshake time for enhanced interoperability with camcorders while unpowered and connected to the bus, will not drive tpbias on a connected port even if receiving incoming bias voltage on that port does not require external filter capacitor for pll supports phy core-link interface initialization and reset supports link-on as a part of the internal phy core-link interface 25 mhz crystal oscillator and internal pll provide transmit/receive data at 100 mbits/s, 200 mbits/s, and 400 mbits/s, and internal link-layer controller clock at 50 mhz interoperable across 1394 cable with 1394 phys- ical layers (phy core) using 5 v supplies node power-class information signaling for system power management supports ack-accelerated arbitration and fly-by concatenation supports arbitrated short bus reset to improve utilization of the bus fully supports suspend/resume supports connection debounce supports multispeed packet concatenation supports phy pinging and remote phy access packets reports cable power fail interrupt when voltage at cps pin falls below 7.5 v separate cable bias and driver termination voltage supply for each port n link: cycle master and isochronous resource manager capable supports 1394a-2000 acceleration features
2 agere systems inc. fw323 05 data sheet, rev. 2 1394a pci phy/link open host controller interface october 2001 table of contents contents page features ....................................................................................................................... ............................................1 fw323 functional overview ........................................................................................................ ............................7 other features .................................................................................................................. .......................................7 fw323 functional description ..................................................................................................... ......................7 pci core ........................................................................................................................ ....................................7 isochronous data transfer ........................................................................................................ ........................8 asynchronous data transfer ....................................................................................................... ......................8 asynchronous register ........................................................................................................... ...........................8 serial eeprom interface .......................................................................................................... ........................9 link core ....................................................................................................................... .....................................9 phy core ........................................................................................................................ ...................................9 pin information ................................................................................................................. ......................................13 application schematic ........................................................................................................... .................................18 internal registers .............................................................................................................. .....................................20 pci configuration registers ...................................................................................................... ......................20 vendor id register ............................................................................................................... ...........................21 device id register ............................................................................................................... ............................22 pci command register ............................................................................................................. ......................23 pci status register .............................................................................................................. ...........................25 class code and revision id register ................................................................................................. .............26 latency timer and class cache line size register ...................................................................................... ..27 header type and bist register ...................................................................................................... ................28 ohci base address register ........................................................................................................ ..................30 pci subsystem identification register ............................................................................................. ................32 pci power management capabilities pointer register .................................................................................. ..32 interrupt line and pin register .................................................................................................... ....................33 min_gnt and max_lat register ...................................................................................................... ............34 pci ohci control register ......................................................................................................... .....................35 capability id and next item pointer register ......................................................................................... .........37 power management capabilities register ............................................................................................ ...........38 power management control and status register ........................................................................................ ....40 power management extension register ............................................................................................... ...........42 ohci registers .................................................................................................................. ..............................43 ohci version register ............................................................................................................ ........................46 guid rom register ................................................................................................................ ........................48 asynchronous transmit retries register ............................................................................................ .............50 csr data register ................................................................................................................ ..........................52 csr compare register ............................................................................................................. ......................54 csr control register ............................................................................................................. .........................56 configuration rom header register ................................................................................................. ..............58 bus identification register ...................................................................................................... .........................60 bus options register ............................................................................................................. ..........................62 guid high register ............................................................................................................... ..........................64 guid low register ................................................................................................................ ..........................66 configuration rom mapping register ................................................................................................ .............68 posted write address low register .................................................................................................. ..............70 posted write address high register ................................................................................................. ..............72 vendor id register ............................................................................................................... ...........................74 host controller control register .................................................................................................. ....................76 self-id count register ........................................................................................................... ..........................80 isochronous receive channel mask high register ...................................................................................... ... 82
agere systems inc. 3 data sheet, rev. 2 fw323 05 october 2001 1394a pci phy/link open host controller interface table of contents (continued) contents page isochronous receive channel mask low register ....................................................................................... ...84 interrupt event register ......................................................................................................... ..........................86 interrupt mask register .......................................................................................................... ..........................89 isochronous transmit interrupt event register ...................................................................................... ..........91 isochronous transmit interrupt mask register ....................................................................................... .........93 isochronous receive interrupt event register ....................................................................................... ..........94 isochronous receive interrupt mask register ........................................................................................ .........96 fairness control register ........................................................................................................ ........................97 link control register ............................................................................................................ ............................99 node identification register ..................................................................................................... ......................101 phy core layer control register .................................................................................................... ..............103 isochronous cycle timer register .................................................................................................. ...............105 asynchronous request filter high register .......................................................................................... ........107 asynchronous request filter low register ........................................................................................... ........110 physical request filter high register .............................................................................................. ..............113 physical request filter low register ............................................................................................... .............116 asynchronous context control register ............................................................................................. ...........119 asynchronous context command pointer register ...................................................................................... .121 isochronous transmit context control register ...................................................................................... ......123 isochronous transmit context command pointer register ...........................................................................125 isochronous receive context control register ....................................................................................... ......127 isochronous receive context command pointer register ............................................................................129 isochronous receive context match register ......................................................................................... ......131 fw323 vendor specific registers ................................................................................................... ..............133 isochronous dma control .......................................................................................................... ....................134 asynchronous dma control ......................................................................................................... ..................135 link options .................................................................................................................... ...............................136 crystal selection considerations ................................................................................................. .........................138 load capacitance ................................................................................................................ ..........................138 board layout .................................................................................................................... ..............................138 absolute maximum ratings ......................................................................................................... .........................138 electrical characteristics ...................................................................................................... ................................139 timing characteristics .......................................................................................................... ................................141 ac characteristics of serial eeprom interface signals ................................................................................ ......141 internal register configuration .................................................................................................. ...........................144 phy core register map for cable environment .......................................................................................... .. 144 phy core register fields for cable environment ....................................................................................... ..145 outline diagrams ................................................................................................................ ..................................150 128-pin tqfp .................................................................................................................... ............................150 figure page figure 1. fw323 functional block diagram ............................................................................................ .................7 figure 2. phy core block diagram .................................................................................................... ....................12 figure 3. pin assignments for fw323 ................................................................................................. ...................13 figure 4. application schematic for fw323 ........................................................................................... ................19 figure 5. bus timing .............................................................................................................. ..............................142 figure 6. write cycle timing ....................................................................................................... .........................142 figure 7. data validity ........................................................................................................... ...............................142 figure 8. start and stop definition ................................................................................................. ......................143 figure 9. output acknowledge ...................................................................................................... .......................143
4 4 agere systems inc. fw323 05 data sheet, rev. 2 1394a pci phy/link open host controller interface october 2001 table of contents (continued) table page table 1. pin descriptions ......................................................................................................... ...............................14 table 2. bit-field access tag description ........................................................................................... ...................20 table 3. pci configuration register map ............................................................................................. ..................20 table 4. vendor id register ........................................................................................................ ...........................21 table 5. device id register ........................................................................................................ ............................22 table 6. pci command register ...................................................................................................... ......................23 table 7. pci command register description ........................................................................................... ..............24 table 8. pci status register ....................................................................................................... ...........................25 table 9. class code and revision id register .......................................................................................... ...........26 table 10. class code and revision id register description .............................................................................. ...27 table 11. latency timer and class cache line size register .............................................................................. 27 table 12. latency timer and class cache line size register description ..........................................................28 table 13. header type and bist register .............................................................................................. ..............28 table 14. header type and bist register description ................................................................................... ......29 table 15. ohci base address register ................................................................................................ .................30 table 16. ohci base address register description ..................................................................................... .........31 table 17. pci subsystem identification register description .......................................................................... ......32 table 18. pci power management capabilities pointer register .......................................................................... 32 table 19. interrupt line and pin register ............................................................................................ ...................33 table 20. interrupt line and pin register description ................................................................................. ...........33 table 21. min_gnt and max_lat register .............................................................................................. ...........34 table 22. min_gnt and max_lat register description ................................................................................... ...34 table 23. pci ohci control register ................................................................................................. ...................35 table 24. pci ohci control register description ...................................................................................... ............36 table 25. capability id and next item pointer register ................................................................................. ........37 table 26. capability id and next item pointer register description ...................................................................... 37 table 27. power management capabilities register .................................................................................... .........38 table 28. power management capabilities register description ......................................................................... .39 table 29. power management control and status register ................................................................................ .40 table 30. power management control and status register description ...............................................................41 table 31. power management extension register ....................................................................................... .........42 table 32. power management extension register description ............................................................................ 42 table 33. ohci register map ........................................................................................................ ........................43 table 34. ohci version register .................................................................................................... .......................46 table 35. ohci version register description ......................................................................................... ...............47 table 36. guid rom register ........................................................................................................ ......................48 table 37. guid rom register description ............................................................................................. ...............49 table 38. asynchronous transmit retries register .................................................................................... ..........50 table 39. asynchronous transmit retries register description ......................................................................... ...51 table 40. csr data register ........................................................................................................ .........................52 table 41. csr data register description ............................................................................................. .................53 table 42. csr compare register ..................................................................................................... .....................54 table 43. csr compare register description .......................................................................................... .............55 table 44. csr control register ..................................................................................................... ........................56 table 45. csr control register description .......................................................................................... ...............57 table 46. configuration rom header register ......................................................................................... .............58 table 47. configuration rom header register description .............................................................................. ....59 table 48. bus identification register .............................................................................................. ........................60 table 49. bus identification register description ................................................................................... ................61 table 50. bus options register ..................................................................................................... .........................62 table 51. bus options register description .......................................................................................... .................63
agere systems inc. 5 data sheet, rev. 2 fw323 05 october 2001 1394a pci phy/link open host controller interface table of contents (continued) table page table 52. guid high register ....................................................................................................... .........................64 table 53. guid high register description ............................................................................................ .................65 table 54. guid low register ........................................................................................................ .........................66 table 55. guid low register description ............................................................................................. .................67 table 56. configuration rom mapping register ........................................................................................ ............68 table 57. configuration rom mapping register description ............................................................................. ....69 table 58. posted write address low register .......................................................................................... .............70 table 59. posted write address low register description ............................................................................... .....71 table 60. posted write address high register ......................................................................................... .............72 table 61. posted write address high register description .............................................................................. .....73 table 62. vendor id register ....................................................................................................... ..........................74 table 63. vendor id register description ............................................................................................ ..................75 table 64. host controller control register .......................................................................................... ...................76 table 65. host controller control register description ............................................................................... ...........77 table 66. self-id buffer pointer register ........................................................................................... ....................78 table 67. self-id buffer pointer register description ................................................................................ ............79 table 68. self-id count register ................................................................................................... .........................80 table 69. self-id count register description ........................................................................................ .................81 table 70. isochronous receive channel mask high register .............................................................................. .82 table 71. isochronous receive channel mask high register description ............................................................83 table 72. isochronous receive channel mask low register ............................................................................... .84 table 73. isochronous receive channel mask low register description ............................................................85 table 74. interrupt event register ................................................................................................. .........................86 table 75. interrupt event register description ...................................................................................... .................87 table 76. interrupt mask register .................................................................................................. ........................89 table 77. interrupt mask register description ....................................................................................... ................90 table 78. isochronous transmit interrupt event register .............................................................................. ........91 table 79. isochronous transmit interrupt event register description ................................................................... 92 table 80. isochronous transmit interrupt mask register ............................................................................... ........93 table 81. isochronous receive interrupt event register ............................................................................... ........94 table 82. isochronous receive interrupt event description ............................................................................ ......95 table 83. isochronous receive interrupt mask register ................................................................................ ........96 table 84. fairness control register ................................................................................................ .......................97 table 85. fairness control register description ..................................................................................... ...............98 table 86. link control register .................................................................................................... .........................99 table 87. link control register description ......................................................................................... ...............100 table 88. node identification register ............................................................................................. ....................101 table 89. node identification register description .................................................................................. ............102 table 90. phy core layer control register ............................................................................................ ............103 table 91. phy core layer control register description ................................................................................. ....104 table 92. isochronous cycle timer register .......................................................................................... .............105 table 93. isochronous cycle timer register description ............................................................................... .....106 table 94. asychronous request filter high register ................................................................................... .......107 table 95. asynchronous request filter high register description ......................................................................1 08 table 96. asynchronous request filter low register ................................................................................... .....110 table 97. asynchronous request filter low register description ......................................................................11 1 table 98. physical request filter high register ...................................................................................... ............113 table 99. physical request filter high register description ........................................................................... ....114 table 100. physical request filter low register ...................................................................................... ..........116 table 101. physical request filter low register description ........................................................................... ...117 table 102. asynchronous context control register .................................................................................... ........119
6 6 agere systems inc. fw323 05 data sheet, rev. 2 1394a pci phy/link open host controller interface october 2001 table of contents (continued) table page table 103. asynchronous context control register description ........................................................................1 20 table 104. asynchronous context command pointer register ..........................................................................121 table 105. asynchronous context command pointer register description ........................................................122 table 106. isochronous transmit context control register ............................................................................. ....123 table 107. isochronous transmit context control register description .............................................................124 table 108. isochronous transmit context command pointer register ...............................................................125 table 109. isochronous transmit context command pointer register description ............................................126 table 110. isochronous receive context control register .............................................................................. ....127 table 111. isochronous receive context control register description ...............................................................128 table 112. isochronous receive context command pointer register ................................................................129 table 113. isochronous receive context command pointer register description .............................................130 table 114. isochronous receive context match register ................................................................................ ...131 table 115. isochronous receive context match register description ................................................................132 table 116. fw323 vendor specific registers description ............................................................................... ....133 table 117. isochronous dma control registers description ............................................................................. ..134 table 118. asynchronous dma control registers description ............................................................................ 135 table 119. link registers description .............................................................................................. ....................136 table 120. rom format description .................................................................................................. ..................137 table 121. absolute maximum ratings ................................................................................................ ................138 table 122. analog characteristics ................................................................................................. .......................139 table 123. driver characteristics ................................................................................................. ........................140 table 124. device characteristics ................................................................................................. .......................140 table 125. switching characteristics .............................................................................................. .....................141 table 126. clock characteristics .................................................................................................. ........................141 table 127. ac characteristics of serial eeprom interface signals ....................................................................141 table 128. phy core register map for the cable environment ..........................................................................144 table 129. phy core register fields for cable environment .............................................................................. 145 table 130. phy core register page 0: port status page ................................................................................... 147 table 131. phy core register port status page fields ................................................................................... ..148 table 132. phy core register page 1: vendor identification page ....................................................................149 table 133. phy core register vendor identification page fields .......................................................................14 9
agere systems inc. 7 data sheet, rev. 2 fw323 05 october 2001 1394a pci phy/link open host controller interface fw323 functional overview n pci: revision 2.2 compliant 33 mhz/32-bit operation programmable burst size for pci data transfer supports pci bus power management interface specification v.1.1 supports clockrun protocol per pci mobile design guide global byte swap function other features n i 2 c serial rom interface n cmos process n 3.3 v operation, 5 v tolerant inputs n 128-pin tqfp package the fw323 is the agere systems inc. implementation of a high-performance, pci bus-based open host controller for implementation of ieee 1394a-2000 compliant systems and devices. link-layer functions are handled by the fw323, utilizing the on-chip 1394a-2000 compliant link core and physical layer core. a high-performance and cost- effective solution for connecting and servicing multiple ieee 1394 (both 1394-1995 and 1394a-2000) peripheral devices can be realized. 5-6250 (f).e figure 1. fw323 functional block diagram pci bus cable port 2 pci rom ohci ohci link core isoch async i/f core phy core cable port 1 cable port 0 fw323 functional description the fw323 is comprised of five major functional sections (see figure 1): pci core, isochronous data transfer, asynchronous data transfer, link core, and phy core. the following is a general description of each of the five major sections. pci core the pci core serves as the interface to the pci bus. it contains the state machines that allow the fw323 to respond properly when it is the target of the transaction. during 1394 packet transmission or reception, the pci core arbitrates for the pci bus and enables the fw323 to become the bus master for reading the different buffer descriptors and management of the actual data transfers to/from host system memory. the pci core also supports the pci bus power management interface specification v.1.1. included in this support is a standard power management register interface accessible through the pci configuration space. through this register interface, software is able to transition the fw323 into four distinct power consumption states (d0, d1, d2, and d3). this permits software to selectively increase/decrease the power consumption of the fw323 for reasons such as periods of system inactivity or power conservation. in addition, the fw323 also includes support for hardware wake-up mechanisms through power management events
8 agere systems inc. fw323 05 data sheet, rev. 2 1394a pci phy/link open host controller interface october 2001 fw323 functional description (continued) (pmes). when the fw323 is in a low-power state, pmes provide a hardware mechanism for requesting a software wake-up. together, the power management register interface and pme support within the fw323 combine to form an efficient means for implementing power management. isochronous data transfer the isochronous data transfer logic handles the transfer of isochronous data between the link core and the pci interface module. it consists of the isochronous register module, the isochronous transmit dma module, the isochronous receive dma module, the isochronous transmit fifo, and the isochronous receive fifo. isochronous register the isochronous register module operates on pci slave accesses to ohci registers within the isochronous block. the module also maintains the status of inter- rupts generated within the isochronous block and sends the isochronous interrupt status to the ohci interrupt handler block. isochronous transmit dma (itdma) the isochronous transmit dma module moves data from host memory to the link core, which will then send the data to the 1394 bus. it consists of isochronous contexts, each of which is independently controlled by software, and can send data on a 1394 isochronous channel. during each 1394 isochronous cycle, the itdma module will service each of the contexts and attempt to process one 1394 packet for each context. if a context is active, itdma will request access to the pci bus. when granted pci access, a descriptor block is fetched from host memory. this data is decoded by itdma to determine how much data is required and where in host memory the data resides. itdma initiates another pci access to fetch this data, which is placed into the transmit fifo for processing by the link core.ifthecontextisnotactive,itisskippedbyitdma for the current cycle. after processing each context, itdma writes a cycle marker word in the transmit fifo to indicate to the link core that there is no more data for this isochronous cycle. as a summary, the major steps for the fw323 itdma to transmit a packet are the following: 1. fetch a descriptor block from host memory. 2. fetch data specified by the descriptor block from host memory and place it into the isochronous transmit fifo. 3. data in fifo is read by the link and sent to the phy core device interface. isochronous receive dma (irdma) the isochronous receive dma module moves data from the receive fifo to host memory. it consists of isochronous contexts, each of which is independently controlled by software. normally, each context can process data on a single 1394 isochronous channel. however, software can select one context to receive data on multiple channels. when irdma detects that the link core has placed data into the receive fifo, it immediately reads out the first word in the fifo, which makes up the header of the isochronous packet. irdma extracts the channel number for the packet and packet filtering controls from the header. this information is compared with the control registers for each context to determine if any context is to process this packet. if a match is found, irdma will request access to the pci bus. when granted pci access, a descriptor block is fetched from host memory. the descriptor provides information about the host memory block allocated for the incoming packet. irdma then reads the packet from the receive fifo and writes the data to host memory via the pci bus. if no match is found, irdma will read the remainder of the packet from the receive fifo, but not process the data in any way. asynchronous data transfer the async block is functionally partitioned into two independent logic blocks for transmitting and receiving 1394 packets. the async_tx unit is responsible for packet transmission while the async_rx unit pro- cesses received data. asynchronous register the asynchronous register module operates on pci slave accesses to ohci registers within the asynchro- nous block. the module also maintains the status of interrupts generated within the asynchronous block and sends the asynchronous interrupt status to the ohci interrupt handler block.
agere systems inc. 9 data sheet, rev. 2 fw323 05 october 2001 1394a pci phy/link open host controller interface fw323 functional description (continued) asynchronous transmit (async_tx) the async_tx block of the fw323 manages the asynchronous transmission of either request or response packets. the mechanism for asynchronous transmission of requests and responses are similar. the only difference is the system memory location of the buffer descriptor list when processing the two contexts. therefore, the discussion below, which is for asynchronous transmit requests, parallels that of the asynchronous transmit response. the fw323 asyn- chronous transmission of packets involves the following steps: 1. fetch complete buffer descriptor block from host memory. 2. get data from system memory and store into async fifo. 3. request transfer of data from fifo to link device. 4. handle retries, if any. 5. handle errors in steps 1 to 4. 6. end the transfer if there are no errors. asynchronous receive (async_rx) the async_rx block of the fw323 manages the processing of received packets. data packets are parsed and stored in a dedicated asynchronous receive fifo. command descriptors are read through the pci interface to determine the disposition of the data arriving through the 1394 link. the header of the received packet is processed to determine, among other things, the following: 1. the type of packet received. 2. the source and destinations. 3. the data and size, if any. 4. the operation required, if any. for example, com- pare and swap operation. the async block also handles dma transfers of self- id packets during the 1394 bus initialization phase and block transactions associated with physical request. serial eeprom interface the fw323 features an i 2 c compliant serial rom interface that allows for the connection of an external serial eeprom. the interface provides a mechanism to store configuable data such as the global unique identification (guid) within an external eeprom. the interface consists of the rom_ad and rom_clk pins. rom_clk is an output clock provided by the fw323 to the external eeprom. rom_ad is bidirectional and is used for serial data/control transfer between the fw323 and the external eeprom. the fw323 uses this interface to read the contents of the serial eeprom during initial power-up or when a hardware reset occurs. the fw323 also makes the serial rom interface visible to software through the ohci defined guid rom register. when the fw323 is operational, the guid rom register allows software to initiate reads to the external eeprom. link core it is the responsibility of the link to ascertain if a received packet is to be forwarded to the ohci for processing. if so, the packet is directed to a proper inbound fifo for either the isochronous block or the asynchronous block to process. the link is also responsible for crc generation on outgoing packets and crc checking on receiving packets. to become aware of data to be sent outbound on 1394 bus, the link must monitor the ohci fifos looking for packets in need of transmission. based on data received from the ohci block, the link will form packet headers for the 1394 bus. the link will alert the phy core as to the availability of the outbound data. it is the links function to generate crc for the outbound data. the link also provides phy core register access for the ohci. phy core the phy core provides the analog physical layer func- tions needed to implement a three-port node in a cable-based ieee 1394-1995 and ieee 1394a-2000 network. each cable port incorporates two differential line trans- ceivers. the transceivers include circuitry to monitor the line conditions as needed for determining connec- tion status, for initialization and arbitration, and for packet reception and transmission. the phy core interfaces with the link core. the phy core requires either an external 24.576 mhz crystal or crystal oscillator. the internal oscillator drives an internal phase-locked loop (pll), which gen- erates the required 400 mhz reference signal. the 400 mhz reference signal is internally divided to pro- vide the 49.152 mhz, 98.304 mhz, and 196.608 mhz clock signals that control transmission of the outbound clock signal is also supplied to the associated llc for synchronization of the two chips and is used for resyn- chronization of the received data.
10 agere systems inc. fw323 05 data sheet, rev. 2 1394a pci phy/link open host controller interface october 2001 fw323 functional description (continued) the phy/link interface is a direct connection and does not provide isolation. data bits to be transmitted through the cable ports are received from the llc on two, four, or eight data lines (d[0:7]), and are latched internally in the phy in syn- chronization with the 49.152 mhz system clock. these bits are combined serially, encoded, and transmitted at 98.304 mbits/s, 196.608 mbits/s, or 393.216 mbits/s as the outbound data-strobe information stream. during transmission, the encoded data information is transmit- ted differentially on the tpa and tpb cable pair(s). during packet reception, the tpa and tpb transmit- ters of the receiving cable port are disabled, and the receivers for that port are enabled. the encoded data information is received on the tpa and tpb cable pair. the received data-strobe information is decoded to recover the receive clock signal and the serial data bits. the serial data bits are split into two, four, or eight parallel streams, resynchronized to the local system clock, and sent to the associated llc. the received data is also transmitted (repeated) out of the other active (connected) cable ports. both the tpa and tpb cable interfaces incorporate differential comparators to monitor the line states during initialization and arbitration. the outputs of these comparators are used by the internal logic to determine the arbitration status. the tpa channel monitors the incoming cable common-mode voltage. the value of this common-mode voltage is used during arbitration to set the speed of the next packet transmission. in addition, the tpb channel monitors the incoming cable common-mode voltage for the presence of the remotely supplied twisted-pair bias voltage. this monitor is called bias-detect. the tpbias circuit monitors the value of incoming tpa pair common-mode voltage when local tpbias is inactive. because this circuit has an internal current source and the connected node has a current sink, the monitored value indicates the cable connection status. the monitor is called connect-detect. both the tpb bias-detect monitor and tpbias connect-detect monitor are used in suspend/resume signaling and cable connection detection. the phy core provides a 1.86 v nominal bias voltage for driver load termination. this bias voltage, when seen through a cable by a remote receiver, indicates the presence of an active connection. the value of this bias voltage has been chosen to allow interoperability between transceiver chips operating from 5 v or 3 v nominal supplies. this bias voltage source should be stabilized by using an external filter capacitor of approximately 0.33 f. the port transmitter circuitry and the receiver circuitry are disabled when the port is disabled, suspended, or disconnected. the line drivers in the phy core operate in a high- impedance current mode and are designed to work with external 112 w line-termination resistor networks. one network is provided at each end of each twisted pair cable. each network is composed of a pair of series-connected 56 w resistors. the midpoint of the pair of resistors that is directly connected to the twisted pair a (tpa) signals is connected to the tpbias voltage signal. the midpoint of the pair of resistors that is directly connected to the twisted-pair b (tpb) signals is coupled to ground through a parallel rc network with recommended resistor and capacitor values of 5 k w and 220 pf, respectively. the value of the external resistors are specified to meet the draft standard specifications when connected in parallel with the internal receiver circuits. the driver output current, along with other internal operating currents, is set by an external resistor. this resistor is connected between the r0 and r1 signals and has a value of 2.49 k w 1%. four signals are used as inputs to set four configuration status bits in the self-identification (self- id) packet. these signals are hardwired high or low as a function of the equipment design. pc[0:2] are the three signals that indicate either the need for power from the cable or the ability to supply power to the cable. the fourth signal (contender), as an input, indicates whether a node is a contender for bus manager. when the contender signal is asserted, it means the node is a contender for bus manager. when the signal is not asserted, it means that the node is not a contender. the contender bit corresponds to bit 20 in the self-id packet, pc0 corresponds to bit 21, pc1 corresponds to bit 22, and pc2 corresponds to bit 23 (see table 4-29 of the ieee 1394-1995 standard for additional details). when the power supply of the phy core is removed while the twisted-pair cables are connected, the phy core transmitter and receiver circuitry has been designed to present a high impedance to the cable in order to not load the tpbias signal voltage on the other end of the cable. for reliable operation, the tpb signals must be terminated using the normal termination network,
agere systems inc. 11 data sheet, rev. 2 fw323 05 october 2001 1394a pci phy/link open host controller interface fw323 functional description (continued) regardless of whether a cable is connected to port or not connected to a port. for those applications, when fw323 is used with one or more of the ports not brought out to a connector, those unused ports may be left unconnected without normal termination. when a port does not have a cable connected, internal connect-detect circuitry will keep the port in a disconnected state. note: all gap counts on all nodes of a 1394 bus must be identical. this may be accomplished by using phy core configuration packets (see section 4.3.4.3 of ieee 1394-1995 standard) or by using two bus resets, which resets the gap counts to the maximum level (3fh). the internal link power status (lps) signal works with the internal linkon signal to manage the llc power usage of the node. the lps signal indicates that the llc of the node is powered up or down. if lps is inactive for more than 1.2 s and less than 25 s, the internal phy/link interface is reset. if lps is inactive for greater than 25 s, the phy will disable the internal phy/link interface to save power. the fw323 continues its repeater function. if the phy then receives a link-on packet, the internal linkon sig- nal is activated to output a 6.114 mhz signal, which can be used by the llc to power itself up. once the llc is powered up, the internal lps signal communicates this to the phy and the internal phy/link interface is enabled. internal linkon signal is turned off when lctrl bit is set. three of the signals are used to set up various test conditions used in manufacturing. these signals (se, sm, and ptest) should be connected to v ss for normal operation.
12 12 agere systems inc. fw323 05 data sheet, rev. 2 1394a pci phy/link open host controller interface october 2001 fw323 functional description (continued) 5-5459.i(f) r.01 figure 2. the phy core block diagram link interface i/o received data decoder/ arbitration and control retimer state machine logic bias voltage and current generator cable port 1 cable port 2 oscillator, pll system, and clock generator transmit data encoder cable port 0 tpa0+ tpa0C tpb0+ tpb0C r0 tpbias2 r1 tpbias0 tpbias1 tpa1+ tpa1C tpb1+ tpb1C tpa2+ tpa2C tpb2+ tpb2C xi xo cps lps sysclk lreq ctl0 ctl1 d0 d1 d2 d3 contender se sm resetn crystal d4 d5 d6 d7 pc0 pc1 pc2 linkon
agere systems inc. 13 data sheet, rev. 2 fw323 05 october 2001 1394a pci phy/link open host controller interface pin information 5-7838 (f)a note: active-low signals within this document are indicated by an n following the symbol names. figure 3. pin assignments for the fw323 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 vdd vss cardbusn nc cna nandtree test1 rom_clk rom_ad test0 vdd vss clkrunn pci_intan pci_rstn pci_gntn pci_reqn pci_pmen vdd pci_clk vss pci_ad[31] pci_ad[30] pci_ad[29] pci_ad[28] vdd vss pci_ad[27] pci_ad[26] pci_ad[25] pci_ad[24] vss pci_cben[3] pci_idsel pci_ad[23] pci_ad[22] vdd vss 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 pci_ad[21] pci_ad[20] pci_ad[18] vdd vss pci_ad[17] pci_ad[16] pci_cben[2] pci_framen vdd vss pci_irdyn pci_trdyn pci_devseln pci_stopn vdd vss pci_perrn pci_serrn pci_par pci_cben[1] vss pci_ad[15] pci_ad[14] pci_ad[13] pci_ad[12] vss pci_ad[11] pci_ad[10] pci_ad[9] pci_ad[8] vss vdd pci_cben[0] pci_ad[7] pci_ad[6] pci_ad[5] vss pci_ad[4] pci_ad[3] pci_ad[2] vss vdd pci_ad[1] pci_ad[0] pci_vios contender pc2 pc1 pc0 lkon lps nc vdd cps vssa vdda tpb2C tpb2+ tpa2C tpa2+ tpbias2 vssa 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 vssa vdda tpb1C tpb1+ tpa1C tpa1+ tpbias1 tpb0+ tpa0C tpa0+ tpbias0 vssa vdda r0 r1 pllvdd pllvss xi xo resetn ptest sm se nc nc 104 tpb0C pci_ad[19]
14 14 agere systems inc. fw323 05 data sheet, rev. 2 1394a pci phy/link open host controller interface october 2001 pin information (continued) table 1. pin descriptions pin symbol* * active-low signals within this document are indicated by an n following the symbol names. type description 1vdd power. 2vss ground. 3 cardbusn i cardbusn (active-low). selects mode of operation for pci output buffers. tie low for cardbus operation, high for pci operation. an internal pull-up is provided to force buffers to pci mode, if no connection is made to this pin. 4nc no connect. 5 cna o cable not active. cna output is provided for use in legacy power management systems. 6nandtree o nand tree test output. when the chip is placed into the nand tree test mode, the pin is the output of the nand tree logic. this pin is not used during functional operation. 7test1 i test. used for device testing. tie to vss. 8 rom_clk i/o rom clock. 9rom_ad i/o rom address/data. 10 test0 i test. used for device testing. tie to vss. 11 vdd power. 12 vss ground. 13 clkrunn i/o clkrunn (active-low). optional signal for pci mobile environment. if not used, clkrunn pin needs to be pulled down to vss for correct operation. 14 pci_intan o pci interrupt (active-low). 15 pci_rstn i pci reset (active-low). 16 pci_gntn i pci grant signal (active-low). 17 pci_reqn o pci request signal (active-low). 18 pci_pmen o pci power management event (active-low). 19 vdd power. 20 pci_clk i pci clock input. 33 mhz. 21 vss ground. 22 pci_ad[31] i/o pci address/data bit. 23 pci_ad[30] i/o pci address/data bit. 24 pci_ad[29] i/o pci address/data bit. 25 pci_ad[28] i/o pci address/data bit. 26 vdd power. 27 vss ground. 28 pci_ad[27] i/o pci address/data bit. 29 pci_ad[26] i/o pci address/data bit. 30 pci_ad[25] i/o pci address/data bit. 31 pci_ad[24] i/o pci address/data bit. 32 vss ground. 33 pci_cben[3] i/o pci command/byte enable (active-low). 34 pci_idsel i pci id select. 35 pci_ad[23] i/o pci address/data bit.
agere systems inc. 15 data sheet, rev. 2 fw323 05 october 2001 1394a pci phy/link open host controller interface pin information (continued) table 1. pin descriptions (continued) pin symbol* * active-low signals within this document are indicated by an n following the symbol names. type description 36 pci_ad[22] i/o pci address/data bit. 37 v dd power. 38 v ss ground. 39 pci_ad[21] i/o pci address/data bit. 40 pci_ad[20] i/o pci address/data bit. 41 pci_ad[19] i/o pci address/data bit. 42 pci_ad[18] i/o pci address/data bit. 43 v dd power. 44 v ss ground. 45 pci_ad[17] i/o pci address/data bit. 46 pci_ad[16] i/o pci address/data bit. 47 pci_cben[2] i/o pci command/byte enable signal (active-low). 48 pci_framen i/o pci frame signal (active-low). 49 v dd power. 50 v ss ground. 51 pci_irdyn i/o pci initiator ready signal (active-low). 52 pci_trdyn i/o pci target ready signal (active-low). 53 pci_devseln i/o pci device select signal (active-low). 54 pci_stopn i/o pcistopsignal(active-low). 55 v dd power. 56 v ss ground. 57 pci_perrn i/o pci parity error signal (active-low). 58 pci_serrn i/o pci system error signal (active-low). 59 pci_par i/o pci parity signal. 60 pci_cben[1] i/o pci command/byte enable signal (active-low). 61 v ss ground. 62 pci_ad[15] i/o pci address/data bit. 63 pci_ad[14] i/o pci address/data bit. 64 pci_ad[13] i/o pci address/data bit. 65 pci_ad[12] i/o pci address/data bit. 66 v ss ground. 67 pci_ad[11] i/o pci address/data bit. 68 pci_ad[10] i/o pci address/data bit. 69 pci_ad[9] i/o pci address/data bit. 70 pci_ad[8] i/o pci address/data bit. 71 v ss ground. 72 v dd power. 73 pci_cben[0] i/o pci command/byte enable signal (active-low). 74 pci_ad[7] i/o pci address/data bit. 75 pci_ad[6] i/o pci address/data bit. 76 pci_ad[5] i/o pci address/data bit. 77 v ss ground. 78 pci_ad[4] i/o pci address/data bit.
16 16 agere systems inc. fw323 05 data sheet, rev. 2 1394a pci phy/link open host controller interface october 2001 pin information (continued) table 1. pin descriptions (continued) pin symbol* * active-low signals within this document are indicated by an n following the symbol names. type description 79 pci_ad[3] i/o pci address/data bit. 80 pci_ad[2] i/o pci address/data bit. 81 v ss ground. 82 v dd power. 83 pci_ad[1] i/o pci address/data bit. 84 pci_ad[0] i/o pci address/data bit. 85 pci_vios pci signaling indicator. (5 v or 3.3 v.) 86 contender i contender. on hardware reset, this input sets the default value of the contender bit indicated during self-id. this bit can be programmed by tying the signal to v dd (high) or to ground (low). 87 pc2 i power-class indicators. on hardware reset, these inputs set the default value of the power class indicated during self-id. these bits can be programmed by tying the signals to v dd (high) or to ground (low). 88 pc1 89 pc0 90 lkon o link on. signal from the internal phy core to the internal link core. this signal is provided as an output for use in legacy power management systems. 91 lps o link power status. signal from the internal link core to the internal phy core. lps is provided as an output for use in legacy power management systems. 92 nc no connect. 93 v dd power. 94 cps i cable power status. cps is normally connected to the cable power through a 400 k w resistor. this circuit drives an internal comparator that detects the presence of cable power. this information is maintained in one internal register and is available to the llc by way of a register read (see ieee 1394a-2000, standard for a high performance serial bus (supplement)). 95 v ssa analog circuit ground. all v ssa signals should be tied together to a low-impedance ground plane. 96 v dda analog circuit power. v dda supplies power to the analog portion of the device. 97 tpb2- analog i/o port 2, port cable pair b. tpb2 is the port b connec- tion to the twisted-pair cable. board traces from each pair of positive and negative differential signal pins should be kept matched and as short as possible to the external load resistors and to the cable connector. 98 tpb2+ 99 tpa2- analog i/o port 2, port cable pair a. tpa2 is the port a connec- tion to the twisted-pair cable. board traces from each pair of positive and negative differential signal pins should be kept matched and as short as possible to the external load resistors and to the cable connector. 100 tpa2+
agere systems inc. 17 data sheet, rev. 2 fw323 05 october 2001 1394a pci phy/link open host controller interface pin information (continued) table 1. pin descriptions (continued) pin symbol* * active-low signals within this document are indicated by an n following the symbol names. type description 101 tpbias2 analog i/o port 2, twisted-pair bias. tpbias2 provides the 1.86 v nominal bias voltage needed for proper opera- tion of the twisted-pair cable drivers and receivers and for sending a valid cable connection signal to the remote nodes. 102 v ssa analog circuit ground. all v ssa signals should be tied together to a low-impedance ground plane. 103 v ssa analog circuit ground. all v ssa signals should be tied together to a low-impedance ground plane. 104 v dda analog circuit ground. v dda supplies power to the analog portion of the device. 105 tpb1C analog i/o port 1, port cable pair b. tpb1 is the port b connec- tion to the twisted-pair cable. board traces from each pair of positive and negative differential signal pins should be kept matched and as short as possible to the external load resistors and to the cable connector. 106 tpb1+ 107 tpa1C analog i/o port 1, port cable pair a. tpa1 is the port a connec- tion to the twisted-pair cable. board traces from each pair of positive and negative differential signal pins should be kept matched and as short as possible to the external load resistors and to the cable connector. 108 tpa1+ 109 tpbias1 analog i/o port 1, twisted-pair bias. tpbias1 provides the 1.86 v nominal bias voltage needed for proper opera- tion of the twisted-pair cable drivers and receivers and for sending a valid cable connection signal to the remote nodes. 110 tpb0C analog i/o port 0, port cable pair b. tpb0 is the port b connec- tion to the twisted-pair cable. board traces from each pair of positive and negative differential signal pins should be kept matched and as short as possible to the external load resistors and to the cable connector. 111 tpb0+ 112 tpa0C analog i/o port 0, port cable pair a. tpa0 is the port a connec- tion to the twisted-pair cable. board traces from each pair of positive and negative differential signal pins should be kept matched and as short as possible to the external load resistors and to the cable connector. 113 tpa0+ 114 tpbias0 analog i/o port 0, twisted-pair bias. tpbias0 provides the 1.86 v nominal bias voltage needed for proper opera- tion of the twisted-pair cable drivers and receivers and for sending a valid cable connection signal to the remote nodes. 115 v ssa analog circuit ground. all v ssa signals should be tied together to a low-impedance ground plane. 116 v dda analog circuit power. v dda supplies power to the analog portion of the device.
18 18 agere systems inc. fw323 05 data sheet, rev. 2 1394a pci phy/link open host controller interface october 2001 pin information (continued) table 1. pin descriptions (continued) application schematic the application schematic presents a complete three-port, 400 mbits/s ieee 1394a-2000 design, featuring the agere fw323 pci bus-based host ohci controller and 400 mbits/s phy core. the fw323 device needs only a power source (u3), connection to pci interface, 1394a-2000 terminators and connectors, crystal, and serial eeprom. no external phy is required because the fw323 contains both host controller and phy core functions. this design is a secondary (class 4) power provider to the 1394 bus, and will participate in the required 1394a- 2000 bus activities, even when power on the pci bus is not energized. pin symbol* * active-low signals within this document are indicated by an n following the symbol names. type description 117 r0 i current setting resistor. an internal reference voltage is applied to a resistor connected between r0 and r1 to set the operating current and the cable driver output current. a low temperature-coefficient resistor (tcr) with a value of 2.49 k w 1% should be used to meet the ieee 1394-1995 standard requirements for output voltage limits. 118 r1 119 pllv dd power for pll circuit. pllv dd supplies power to the pll circuitry portion of the device. 120 pllv ss ground for pll circuit. pllv ss is tied to a low- impedance ground plane. 121 xi crystal oscillator. xi and xo connect to a 24.576 mhz parallel resonant fundamental mode crystal. although when a 24.576 mhz clock source is used, it can be connected to xi with xo left uncon- nected. the optimum values for the external shunt capacitors are dependent on the specifications of the crystal used. the suggested values of 12 pf are appro- priate for crystal with 7 pf specified loads. for more details, see the crystal selection considerations section. 122 xo 123 resetn i reset (active-low). when resetn is asserted low (active), a bus reset condition is set on the active cable ports and the internal phy core logic is reset to the reset start state. an internal pull-up resistor, which is connected to v dd , is provided, so only an external delay capacitor and resistor are required. this input is a standard logic buffer and can also be driven by an open-drain logic output buffer. 124 ptest i test. used for device testing. tie to v ss . 125 sm i test mode control. sm is used during the manufac- turing test and should be tied to v ss . 126 se i test mode control. se is used during the manufac- turing test and should be tied to v ss . 127 nc no connect. 128 nc no connect.
agere systems inc. 19 data sheet, rev. 2 fw323 05 october 2001 1394a pci phy/link open host controller interface application schematic (continued) 5-8886(f) r.05fm figure 4. application schematic for the fw323 ad0 ad1 ad2 ad3 ad4 ad5 ad6 ad7 ad8 ad9 ad10 ad11 ad12 ad13 ad14 ad15 ad16 ad17 ad18 ad19 ad20 ad21 ad22 ad23 ad24 ad25 ad26 ad27 ad28 ad29 ad30 ad31 85 84 83 80 79 78 76 75 74 70 69 68 67 65 64 63 62 46 45 42 41 40 39 36 35 31 30 29 28 25 24 23 22 c_be#0 73 60 47 33 c_be#1 c_be#2 c_be#3 par frame# irdy# trdy# devsel# stop# idsel 59 48 51 52 53 54 34 17 16 57 58 20 13 15 14 18 req# perr# gnt# serr# clk rst# inta# pme# pci_vios pci_ad0 pci_ad1 pci_ad2 pci_ad3 pci_ad4 pci_ad5 pci_ad6 pci_ad7 pci_ad8 pci_ad9 pci_ad10 pci_ad11 pci_ad12 pci_ad13 pci_ad14 pci_ad15 pci_ad16 pci_ad17 pci_ad18 pci_ad19 pci_ad20 pci_ad21 pci_ad22 pci_ad23 pci_ad24 pci_ad25 pci_ad26 pci_ad27 pci_ad28 pci_ad29 pci_ad30 pci_ad31 pci_cben0 pci_cben1 pci_cben2 pci_cben3 pci_par pci_framen pci_irdyn pci_trdyn pci_devseln pci_stopn pci_idsel pci_reqn pci_gntn pci_perrn pci_serrn pci_pclk pci_clkrunn pci_prstn pci_intan pci_pmen 93 82 72 55 49 43 37 26 19 11 1 96 104 116 119 vdd vdd vdd vdd vdd vdd vdd vdd vdd vdd vdd vdda vdda vdda pllvdd tpb0C tpb0+ tpa0C tpa0+ tpbias0 tpb1C tpb1+ tpa1C tpa1+ tpbias1 tpb2C tpb2+ tpa2C tpa2+ tpbias2 111 110 112 113 114 105 106 107 108 109 97 98 99 100 101 cps nc lps lkon pc0 pc1 pc2 contender nc nc cardbusn nc cna nandtree test0 test1 ptest se sm 94 92 91 90 89 88 87 86 128 127 3 4 5 6 10 7 124 126 125 vcc sdata sclk a0 a1 a2 wp gnd at24c02an-2.7 vss vss vss vss vss vss vss vss vss vss vss vss vss vss pllvss vssa vssa vssa vssa rom_ad rom_clk 9 8 x1 x0 resetn r1 r0 pci bus fw323 3.3 v 3.3 v 3.3 va 121 122 123 118 117 c3 y1 24.576 mhz c4 c5 r7 2.49 k w 1% 1/10 w 1 4 3 2 r13 402 k w 1% r14 10 k w r18 10 k w r19 10 k w r20 10 k w bpwr 3.3 v 3.3 v r24 r23 10 k w 10 k w rom_ad rom_clk 3.3 v u2 vout nc nc nc nc nc fb vin nc nc nc on/ off siggnd pwrgnd agnd 2 12 21 27 32 38 44 50 56 61 66 71 77 81 120 115 103 102 95 bpwr 5vpci 12 v pci cr2 mbrs340t3 cr4 mbrs340t3 f4 1.5 a resettable eeprom cr1 mbrs340t3 + c12 22 m f 50 v pwrsrc 10 1 2 7 5 4 6 vp vg tpbC tpb+ tpaC tpa+ agnd 1 2 3 4 5 6 c9 220 pf r15 56.2 w 1% 1/10 w r16 56.2 w 1% 1/10 w r17 4.99 w 1% 1/10 w j3 1394a port 3 agnd agnd c11 0.33 m f f3 omni - block fuse bpwr agnd r21 56.2 w 1% 1/10 w r22 56.2 w 1% 1/10 w vp vg tpbC tpb+ tpaC tpa+ agnd 1 2 3 4 5 6 c7 220 pf r8 56.2 w 1% 1/10 w r9 56.2 w 1% 1/10 w r10 4.99 w 1% 1/10 w j2 1394a port 2 agnd agnd c8 0.33 m f f2 omni - block fuse bpwr agnd r11 56.2 w 1% 1/10 w r12 56.2 w 1% 1/10 w vp vg tpbC tpb+ tpaC tpa+ agnd 1 2 3 4 5 6 c1 220 pf r1 56.2 w 1% 1/10 w r2 56.2 w 1% 1/10 w r3 4.99 w 1% 1/10 w j1 1394a port 1 agnd agnd c6 0.33 m f f1 omni - block fuse bpwr agnd r4 56.2 w 1% 1/10 w r5 56.2 w 1% 1/10 w u3 supplies vddx power; it is sourced by the most positive of pci 5 v, pci 12 v, u3 power plane filtering ground plane c13 100 m f 10 v c14 100 m f 10 v cr3 mbrs1100t3 l1 680 m h ++ agnd 3.3 v 3.3 va lm2574hvm-3.3 0.1 m f 12 pf 12 pf u1 and 1394 bus power (bpwr). 8 5 6 1 2 3 7 4 12 8 9 11 13 14 3 510 k w
20 20 agere systems inc. fw323 05 data sheet, rev. 2 1394a pci phy/link open host controller interface october 2001 internal registers this section describes the internal registers in fw323, including both pci configuration registers and ohci regis- ters. all registers are detailed in the same format; a brief description for each register, followed by the register offset and a bit table describing the reset state for each register. a bit description table indicates bit-field names, a detailed field description, and field access tags. table 2 describes the field access tags. table 2. bit-field access tag description pci configuration registers table 3 illustrates the pci configuration header that includes both the predefined portion of the configuration space and the user definable registers. table 3. pci configuration register map access tag name description r read field may be read by software. w write field may be written by software to any value. s set field may be set by a write of 1. writes of 0 have no effect. c clear field may be cleared by a write of 1. writes of 0 have no effect. u update field may be autonomously updated by the fw323. register name offset device id vendor id 00h status command 04h class code revision id 08h bist header type latency timer cache line size 0ch ohci registers base address 10h reserved 14h reserved 18h reserved 1ch reserved 20h reserved 24h reserved 28h subsystem id subsystem vendor id 2ch reserved 30h reserved capabilities pointer 34h reserved 38h maximum latency minimum grant interrupt pin interrupt line 3ch pci ohci control register 40h power management capabilities next item pointer capability id 44h pm data pmcsr_bse power management csr 48h reserved 4cfch
agere systems inc. 21 data sheet, rev. 2 fw323 05 october 2001 1394a pci phy/link open host controller interface internal registers (continued) vendor id register the vendor id register contains a value allocated by the pci sig and identifies the manufacturer of the device. the vendor id assigned to agere is 11c1h. table 4. vendor id register register: vendor id register type: read only offset: 00h default: 11c1h bit field name type de fa ult 15 vendor id r 0 14 r 0 13 r 0 12 r 1 11 r 0 10 r 0 9r0 8r1 7r1 6r1 5r0 4r0 3r0 2r0 1r0 0r1
22 22 agere systems inc. fw323 05 data sheet, rev. 2 1394a pci phy/link open host controller interface october 2001 internal registers (continued) device id register the device id register contains a value assigned to the fw323 by agere. the device identification for the fw323 is 5811h. table5.deviceidregister register: device id register type: read only offset: 02h default: 5811h bit field name type de fa ult 15 device id r 0 14 r 1 13 r 0 12 r 1 11 r 1 10 r 0 9r0 8r0 7r0 6r0 5r0 4r1 3r0 2r0 1r0 0r1
agere systems inc. 23 data sheet, rev. 2 fw323 05 october 2001 1394a pci phy/link open host controller interface internal registers (continued) pci command register the command register provides control over the fw323 interface to the pci bus. all bit functions adhere to the definitions in the pci local bus specification, as in the following bit descriptions. table 6. pci command register register: pci command register type: read/write offset: 04h default: 0000h bit field name type default 15 reserved r 0 14 r 0 13 r 0 12 r 0 11 r 0 10 r 0 9fbb_enb r 0 8 serr_enb rw 0 7 step_enb r 0 6 perr_enb rw 0 5vga_enb r 0 4mwi_enbrw 0 3 special r 0 2 master_enb rw 0 1 memory_enb rw 0 0io_enb r0
24 24 agere systems inc. fw323 05 data sheet, rev. 2 1394a pci phy/link open host controller interface october 2001 internal registers (continued) table 7. pci command register description bit field name type description 15:10 reserved r reserved. bits 15:10 return 0s when read. 9fbb_enbr fast back-to-back enable. the fw323 does not generate fast back- to-back transactions; thus, this bit returns 0 when read. 8 serr_enb rw serr enable. when this bit is set, the fw323 serr driver is enabled. serr can be asserted after detecting an address parity error on the pci bus. 7 step_enb r address/data stepping control. the fw323 does not support address/data stepping; thus, this bit is hardwired to 0. 6 perr_enb rw parity error enable. when this bit is set, the fw323 is enabled to drive perr response to parity errors through the perr signal. 5vga_enbr vga palette snoop enable. the fw323 does not feature vga palette snooping. this bit returns 0 when read. 4mwi_enbrw memory write and invalidate enable. when this bit is set, the fw323 is enabled to generate mwi pci bus commands. if this bit is reset, then the fw323 generates memory write commands instead. 3 special r special cycle enable. the fw323 function does not respond to special cycle transactions. this bit returns 0 when read. 2 master_enb rw bus master enable. when this bit is set, the fw323 is enabled to initiate cycles on the pci bus. 1 memory_enb rw memory response enable. setting this bit enables the fw323 to respond to memory cycles on the pci bus. this bit must be set to access ohci registers. 0io_enbr i/o space enable. the fw323 does not implement any i/o mapped functionality; thus, this bit returns 0 when read.
agere systems inc. 25 data sheet, rev. 2 fw323 05 october 2001 1394a pci phy/link open host controller interface internal registers (continued) pci status register the status register provides status over the fw323 interface to the pci bus. all bit functions adhere to the definitions in the pci local bus specification, as in the following bit descriptions. table 8. pci status register register: pci status register type: read/clear/update offset: 06h default: 0210h bit field name type default 15 par_err rcu 0 14 sys_err rcu 0 13 mabort rcu 0 12 tabort_rec rcu 0 11 tabort_sig rcu 0 10 pci_speed r 0 9r1 8 datapar rcu 0 7 fbb_cap r 0 6 udf r 0 5 66mhz r 0 4caplist r 1 3 reserved r 0 2r0 1r0 0r0
26 26 agere systems inc. fw323 05 data sheet, rev. 2 1394a pci phy/link open host controller interface october 2001 internal registers (continued) class code and revision id register the class code register and revision id register categorizes the fw323 as a serial bus controller (0ch), controlling an ieee 1394 bus (00h), with an ohci programming model (10h). furthermore, the chip revision is indicated in the lower byte. table 9. class code and revision id register register: class code and revision id register type: read only offset: 08h default: 0c00 1000h bit field name type default 31 baseclass r 0 30 r 0 29 r 0 28 r 0 27 r 1 26 r 1 25 r 0 24 r 0 23 subclass r 0 22 r 0 21 r 0 20 r 0 19 r 0 18 r 0 17 r 0 16 r 0 15 pgmif r 0 14 r 0 13 r 0 12 r 1 11 r 0 10 r 0 9r0 8r0 7 chiprev r 0 6r0 5r0 4r0 3r0 2r0 1r0 0r0
agere systems inc. 27 data sheet, rev. 2 fw323 05 october 2001 1394a pci phy/link open host controller interface internal registers (continued) table 10. class code and revision id register description latencytimerandclasscachelinesizeregister the latency timer and class cache line size register is programmed by host bios to indicate system cache line size and the latency timer associated with the fw323. table 11. latency timer and class cache line size register register: latency timer and class cache line size register type: read/write offset: 0ch default: 0000h bit field name type description 31:24 baseclass r base class. this field returns 0ch when read, which classifies the func- tion as a serial bus controller. 23:16 subclass r subclass. this field returns 00h when read, which specifically classifies the function as an ieee 1394 serial bus controller. 15:8 pgmif r programming interface. this field returns 10h when read, indicating that the programming model is compliant with the 1394 open host controller interface specification . 7:0 chiprev r silicon revision. this field returns 04h when read, indicating the silicon revision of the fw323. bit field name type de fault 15 latency_timer rw 0 14 rw 0 13 rw 0 12 rw 0 11 rw 0 10 rw 0 9rw0 8rw0 7 cacheline_sz rw 0 6rw0 5rw0 4rw0 3rw0 2rw0 1rw0 0rw0
28 28 agere systems inc. fw323 05 data sheet, rev. 2 1394a pci phy/link open host controller interface october 2001 internal registers (continued) table 12. latency timer and class cache line size register description header type and bist register the header type and bist register indicates the fw323 pci header type, and indicates no built-in self-test. table 13. header type and bist register register: header type and bist register type: read only offset: 0eh default: 0000h bit field name type description 15:8 latency_timer rw pci latency timer. the value in this register specifies the latency timer for the fw323, in units of pci clock cycles. when the fw323 is a pci bus initiator and asserts frame, the latency timer begins counting from zero. if the latency timer expires before the fw323 transaction has terminated, then the fw323 terminates the transac- tion when its gnt is deasserted. 7:0 cacheline_sz rw cachelinesize. this value is used by the fw323 during memory write and invalidate, memory read line, and memory read multiple transactions. bit field name type default 15 bist r 0 14 r 0 13 r 0 12 r 0 11 r 0 10 r 0 9r0 8r0 7 header_type r 0 6r0 5r0 4r0 3r0 2r0 1r0 0r0
agere systems inc. 29 data sheet, rev. 2 fw323 05 october 2001 1394a pci phy/link open host controller interface internal registers (continued) table 14. header type and bist register description bit field name type description 15:8 bist r built-in self-test. the fw323 does not include a built-in self-test; thus, this field returns 00h when read. 7:0 header_type r pci header type. the fw323 includes the standard pci header, and this is communicated by returning 00h when this field is read.
30 30 agere systems inc. fw323 05 data sheet, rev. 2 1394a pci phy/link open host controller interface october 2001 internal registers (continued) ohci base address register the ohci base address register is programmed with a base address referencing the memory-mapped ohci con- trol. when bios writes all 1s to this register, the value read back is ffff f000h, indicating that 4k bytes of mem- ory address space are required for the ohci registers. table 15. ohci base address register register: ohci base address register type: read/write offset: 10h default: 0000 0000h bit field name type default 31 rw ohcireg_ptr 0 30 rw 0 29 rw 0 28 rw 0 27 rw 0 26 rw 0 25 rw 0 24 rw 0 23 rw 0 22 rw 0 21 rw 0 20 rw 0 19 rw 0 18 rw 0 17 rw 0 16 rw 0 15 rw 0 14 rw 0 13 rw 0 12 rw 0 11 rw ohci_sz 0 10 r 0 9r 0 8r 0 7r 0 6r 0 5r 0 4r 0 3 r ohci_pf 0 2 r ohci_memtype 0 1r 0 0 r ohci_mem 0
agere systems inc. 31 data sheet, rev. 2 fw323 05 october 2001 1394a pci phy/link open host controller interface internal registers (continued) table 16. ohci base address register description bit field name type description 31:12 ohcireg_ptr rw ohci register pointer. specifies the upper 20 bits of the 32-bit ohci base address register. 11:4 ohci_sz r ohci register size. this field returns 0s when read, indicating that the ohci registers require a 4 kbyte region of memory. 3 ohci_pf r ohci register prefetch. this bit returns 0 when read, indicating that the ohci registers are nonprefetchable. 2:1 ohci_memtype r ohci memory type. this field returns 0s when read, indicating that the ohci base address register is 32 bits wide and mapping can be done anywhere in the 32-bit memory space. 0ohci_memr ohci memory indicator. this bit returns 0 when read, indicating that the ohci registers are mapped into system memory space.
32 32 agere systems inc. fw323 05 data sheet, rev. 2 1394a pci phy/link open host controller interface october 2001 internal registers (continued) pci subsystem identification register the pci subsystem identification register is used to uniquely identify the card or system in which the fw323 resides. these values are loaded from the serial eeprom during the power-up sequence. table 17. pci subsystem identification register description pci power management capabilities pointer register the pci power management capabilities pointer register provides a pointer into the pci configuration header where the pci power management register block resides. the fw323 configuration words at offsets 44h and 48h provide the power management registers. this register is read only and returns 44h when read. table 18. pci power management capabilities pointer register register: pci power management capabilities pointer register type: read only offset: 34h default: 44h bit field name type description 31:16 ssid ru subsystem id. this field indicates the subsystem id. 15:0 ssvid ru subsystem vendor id. this field indicates the subsystem vendor id. bit type default 7r0 6r1 5r0 4r0 3r0 2r1 1r0 0r0
agere systems inc. 33 data sheet, rev. 2 fw323 05 october 2001 1394a pci phy/link open host controller interface internal registers (continued) interrupt line and pin register the interrupt line and pin register is used to communicate interrupt line routing information. table 19. interrupt line and pin register register: interrupt line and pin register type: read/write offset: 3ch default: 0100h table 20. interrupt line and pin register description bit field name type de fault 15 intr_pin r 0 14 r 0 13 r 0 12 r 0 11 r 0 10 r 0 9r0 8r1 7 intr_line rw 0 6rw0 5rw0 4rw0 3rw0 2rw0 1rw0 0rw0 bit field name type description 15:8 intr_pin r interrupt pin register. this register returns 01h when read, indi- cating that the fw323 pci function signals interrupts on the inta pin. 7:0 intr_line rw interrupt line register. this register is programmed by the system and indicates to software to which interrupt line the fw323 inta is connected.
34 34 agere systems inc. fw323 05 data sheet, rev. 2 1394a pci phy/link open host controller interface october 2001 internal registers (continued) min_gnt and max_lat register the min_gnt and max_lat register is used to communicate to the system the desired setting of the latency timer register. if a serial rom is detected, then the contents of this register are loaded through the serial rom interface after a pci reset. if no serial rom is detected, then this register returns a default value that corresponds to the min_gnt = 0c, max_lat = 18. table 21. min_gnt and max_lat register register: min_gnt and max_lat register type: read/update offset: 3eh default: 180c table 22. min_gnt and max_lat register description bit field name type de fault 15 max_lat ru 0 14 ru 0 13 ru 0 12 ru 1 11 ru 1 10 ru 0 9ru0 8ru0 7 min_gnt ru 0 6ru0 5ru0 4ru0 3ru1 2ru1 1ru0 0ru0 bit field name type description 15:8 max_lat ru maximum latency. the contents of this register may be used by host bios to assign an arbitration priority level to the fw323. the default for this register indicates that the fw323 may need to access the pci bus as often as every 0.25 m s; thus, an extremely high priority level is requested. the contents of this field may also be loaded through the serial rom. 7:0 min_gnt ru minimum grant. the contents of this register may be used by host bios to assign a latency timer register value to the fw323. the default for this register indicates that the fw323 may need to sustain burst transfers for nearly 64 m s; thus, requesting a large value be programmed in the fw323 latency timer register.
agere systems inc. 35 data sheet, rev. 2 fw323 05 october 2001 1394a pci phy/link open host controller interface internal registers (continued) pciohcicontrolregister the pci ohci control register is defined by the 1394 open host controller interface specification and provides a bit for big endian pci support. note that the global_swap bit is loaded from the serial eeprom on powerup. table 23. pci ohci control register register: pci ohci control register type: read/write offset: 40h default: 0000 0000h bit field name type default 31 reserved r 0 30 r 0 29 r 0 28 r 0 27 r 0 26 r 0 25 r 0 24 r 0 23 r 0 22 r 0 21 r 0 20 r 0 19 r 0 18 r 0 17 r 0 16 r 0 15 r 0 14 r 0 13 r 0 12 r 0 11 r 0 10 r 0 9r0 8r0 7r0 6r0 5r0 4r0 3r0 2r0 1r0 0 global_swap rw 0
36 36 agere systems inc. fw323 05 data sheet, rev. 2 1394a pci phy/link open host controller interface october 2001 internal registers (continued) table 24. pci ohci control register description bit field name type description 31:1 reserved r reserved. bits 31:1 return 0s when read. 0 global_swap rw when this bit is set, all quadlets read from and written to the pci inter- face are byte swapped.
agere systems inc. 37 data sheet, rev. 2 fw323 05 october 2001 1394a pci phy/link open host controller interface internal registers (continued) capability id and next item pointer register the capability id and next item pointer register identifies the linked list capability item and provides a pointer to the next capability item. table 25. capability id and next item pointer register register: capability id and next item pointer register type: read only offset: 44h default: 0001h table 26. capability id and next item pointer register description bit field name type de fault 15 next_item r 0 14 r 0 13 r 0 12 r 0 11 r 0 10 r 0 9r0 8r0 7 capability_id r 0 6r0 5r0 4r0 3r0 2r0 1r0 0r1 bit field name type description 15:8 next_item r next item pointer. the fw323 supports only one additional capability that is communicated to the system through the extended capabilities list; thus, this field returns 00h when read. 7:0 capability_id r capability identification. this field returns 01h when read, which is the unique id assigned by the pci sig for pci power management capability.
38 38 agere systems inc. fw323 05 data sheet, rev. 2 1394a pci phy/link open host controller interface october 2001 internal registers (continued) power management capabilities register the power management capabilities register indicates the capabilities of the fw323 related to pci power management. table 27. power management capabilities register register: power management capabilities register type: read/update offset: 46h default: 7e02h bit field name type de fault 15 pme_d3cold r 0 14 pme_d3hot r 1 13 pme_d2 r 1 12 pme_d1 r 1 11 pme_d0 r 1 10 d2_support r 1 9 d1_support r 1 8dyn_datar 0 7 reserved r 0 6r0 5dsir 0 4aux_pwrr 0 3 pme_clk r 0 2 pm_version r 0 1r1 0r0
agere systems inc. 39 data sheet, rev. 2 fw323 05 october 2001 1394a pci phy/link open host controller interface internal registers (continued) table 28. power management capabilities register description bit field name type description 15 pme_d3cold r pme support from d3 cold. set to 0, indicating the fw323 will not generate a pme event in the d3 cold state. 14 pme_d3hot r pme support from d3 hot. set to 1, indicating that the fw323 can generate a pme event in the d3 hot state. 13 pme_d2 r pme support from d2. set to 1, indicating that the fw323 can generate a pme in d2. 12 pme_d1 r pme support from d1. set to 1, indicating that the fw323 can generate a pme in d1. 11 pme_d0 r pme support from d0. set to 1, indicating that the fw323 can generate a pme in d0. 10 d2_support r d2 support. this bit returns a 1 when read, indicating that the fw323 supports the d2 power state. 9 d1_support r d1 support. this bit returns a 1 when read, indicating that the fw323 supports the d1 power state. 8dyn_datar dynamic data support. this bit returns a 0 when read, indicating that the fw323 does not report dynamic power consumption data. 7:6 reserved r reserved. bits 7:6 return 0s when read. 5dsir device-specific initialization. this bit returns 0 when read, indi- cating that the fw323 does not require special initialization beyond the standard pci configuration header before a generic class driver is able to use it. 4aux_pwrr auxiliary power source. since the fw323 does not support pme generation in the d3 cold device state, this bit returns 0 when read. 3pme_clkr pme clock. this bit returns 0 when read, indicating that no host bus clock is required for the fw323 to generate pme. 2:0 pm_version r power management version. this field returns 010b when read, indi- cating that the fw323 is compatible with the registers described in the pci power management interface specification ,rev.1.1.
40 40 agere systems inc. fw323 05 data sheet, rev. 2 1394a pci phy/link open host controller interface october 2001 internal registers (continued) power management control and status register the power management control and status register implements the control and status of the pci power management function. this register is not affected by the internally generated reset caused by the transition from thed3hottod0state. table 29. power management control and status register register: power management control and status register type: read/write/clear offset: 48h default: 0000h bit field name type default 15 pme_sts rc 0 14 data_scale r 0 13 r 0 12 data_selected r 0 11 r 0 10 r 0 9r0 8pme_enbrw 0 7 reserved r 0 6r0 5r0 4dyn_datar 0 3 reserved r 0 2r0 1pwr_staterw 0 0rw0
agere systems inc. 41 data sheet, rev. 2 fw323 05 october 2001 1394a pci phy/link open host controller interface internal registers (continued) table 30. power management control and status register description bit field name type description 15 pme_sts rc this bit is set when the fw323 would normally be asserting the pme signal, independent of the state of the pme_enb bit. this bit is cleared by a writeback of 1, and this also clears the pme signal driven bythefw323.writinga0tothisbithasnoeffect. 14:13 data_scale r this field returns 0s when read, since the fw323 does not report dynamic data. 12:9 data_selected r this field returns 0s when read, since the fw323 does not report dynamic data. 8pme_enbrw pme enable. this bit enables the function to assert pme. if this bit is cleared, then assertion of pme is disabled. 7:5 reserved r reserved. bits 7:5 return 0s when read. 4dyn_datar dynamic data. this bit returns 0 when read, since the fw323 does not report dynamic data. 3:2 reserved r reserved. bits 3:2 return 0s when read. 1:0 pwr_state rw power state. this 2-bit field is used to set the fw323 device power state and is encoded as follows: 00 = current power state is d0. 01 = current power state is d1. 10 = current power state is d2. 11 = current power state is d3.
42 42 agere systems inc. fw323 05 data sheet, rev. 2 1394a pci phy/link open host controller interface october 2001 internal registers (continued) power management extension register the power management extension register provides extended power management features not applicable to the fw323; thus, it is read only and returns 0 when read. table 31. power management extension register register: power management extension register type: read only offset: 4ah default: 0000h table 32. power management extension register description bit field name type de fault 15 pm_data r 0 14 r 0 13 r 0 12 r 0 11 r 0 10 r 0 9r0 8r0 7 pmcsr_bse rw 0 6rw0 5rw0 4rw0 3rw0 2rw0 1rw0 0rw0 bit field name type description 15:8 pm_data r power management data. this field returns 00h when read since the fw323 does not report dynamic data. 7:0 pmcsr_bse r power management csr bridge support extensions. this field returns 00h when read since the fw323 does not provide p2p bridging.
agere systems inc. 43 data sheet, rev. 2 fw323 05 october 2001 1394a pci phy/link open host controller interface internal registers (continued) ohci registers the ohci registers defined by the 1394 open host controller interface specification are memory mapped into a 2 kbyte region of memory pointed to by the ohci base address register at offset 10h in pci configuration space. these registers are the primary interface for controlling the fw323 ieee 1394 ohci function. this section provides the register interface and bit descriptions. there are several set and clear register pairs in this programming model, which are implemented to solve various issues with typical read-modify-write control registers. there are two addresses for a set/clear register: registerset and registerclear. refer to table 33 for an illustration. a 1 bit written to registerset causes the corresponding bit in the set/clear register to be set, while a 0 bit leaves the corresponding bit unaffected. a 1 bit written to registerclear causes the corresponding bit in the set/clear register to be reset, while a 0 bit leaves the corresponding bit in the set/clear register unaffected. typically, a read from either registerset or registerclear returns the contents of the set or clear register. however, sometimes reading the registerclear provides a masked version of the set or clear register. the interrupt event register is an example of this behavior. the following register definitions are based on version 1.0 of the 1394 open host controller specification . these definitions do not include any incremental changes or additions defined in version 1.1 of the 1394 open host controller specification . the version 1.1 changes and additions will be included in a future revision of this data sheet. table 33. ohci register map dma context register name abbreviation offset ohci version version 00h global unique id rom guid_rom 04h asynchronous transmit retries atretries 08h csr data csrdata 0ch csr compare data csrcomparedata 10h csr control csrcontrol 14h configuration rom header configromhdr 18h bus identification busid 1ch bus options busoptions 20h global unique id high guidhi 24h global unique id low guidlo 28h pci subsystem identification ssid 2ch reserved 30h configuration rom map configrommap 34h posted write address low postedwriteaddresslo 38h posted write address high postedwriteaddresshi 3ch vendor identification vendorid 40h capability id and next item pointer cap_id 44h power management capabilities pm_cap 46h power management control and status pmcsr 48h power management extensions pm_ext 4ah reserved 4ch host controller control hccontrolset 50h hccontrolclr 54h reserved 58h reserved 5ch
44 44 agere systems inc. fw323 05 data sheet, rev. 2 1394a pci phy/link open host controller interface october 2001 internal registers (continued) table 33. ohci register map (continued) dma context register name abbreviation offset self-id reserved 60h self-id buffer selfidbuffer 64h self-id count selfidcount 68h reserved 6ch isochronous receive channel mask high irchannelmaskhiset 70h irchannelmaskhiclear 74h isochronous receive channel mask low irchannelmaskloset 78h irchannelmaskloclear 7ch interrupt event inteventset 80h inteventclear 84h interrupt mask intmaskset 88h intmaskclear 8ch isochronous transmit interrupt event isoxmitinteventset 90h isoxmitinteventclear 94h isochronous transmit interrupt mask isoxmitintmaskset 98h isoxmitintmaskclear 9ch isochronous receive interrupt event isorecvinteventset a0h isorecvinteventclear a4h isochronous receive interrupt mask isorecvintmaskset a8h isorecvintmaskclear ach reserved b0h:d8h fairness control fairnesscontrol dch link control linkcontrolset e0h linkcontrolclear e4h node identification nodeid e8h phy core layer control phycontrol ech isochronous cycle timer isocyctimer f0h reserved f4h reserved f8h reserved fch asynchronous request filter high asyncrequestfilterhiset 100h asyncrequestfilterhiclear 104h asynchronous request filter low asyncrequestfilterloset 108h asyncrequestfilterloclear 10ch physical request filter high physicalrequestfilterhiset 110h physicalrequestfilterhiclear 114h physical request filter low physicalrequestfilterloset 118h physicalrequestfilterloclear 11ch physical upper bound physicalupperbound 120h reserved 124h:17ch
agere systems inc. 45 data sheet, rev. 2 fw323 05 october 2001 1394a pci phy/link open host controller interface internal registers (continued) table 33. ohci register map (continued) dma context register name abbreviation offset asychronous request transmit [atrq] context control contextcontrolset 180h contextcontrolclear 184h reserved 188h command pointer commandptr 18ch asychronous response transmit [atrs] reserved 190h19ch context control contextcontrolset 1a0h contextcontrolclear 1a4h reserved 1a8h command pointer commandptr 1ach asychronous request receive [arrq] reserved 1b0h1bch context control contextcontrolset 1c0h contextcontrolclear 1c4h reserved 1c8h command pointer commandptr 1cch asychronous response receive [arrs] reserved 1d0h1dch context control contextcontrolset 1e0h contextcontrolclear 1e4h reserved 1e8h command pointer commandptr 1ech isochronous transmit context n n=0:7 reserved 1f0h1fch context control contextcontrolset 200h + 16 * n contextcontrolclear 204h + 16 * n reserved 208h + 16 * n command pointer commandptr 20ch + 16 * n isochronous receive context n n=0:7 context control contextcontrolset 400h + 32 * n contextcontrolclear 404h + 32 * n reserved 408h + 32 * n command pointer commandptr 40ch + 32 * n context match contextmatch 410h + 32 * n
46 46 agere systems inc. fw323 05 data sheet, rev. 2 1394a pci phy/link open host controller interface october 2001 internal registers (continued) ohci version register this register indicates the ohci version support, and whether or not the serial rom is present. table 34. ohci version register register: ohci version register type: read only offset: 00h default: 0x01 0000h bit field name type de fault 31 reserved r 0 30 r 0 29 r 0 28 r 0 27 r 0 26 r 0 25 r 0 24 guid_rom r x 23 version r 0 22 r 0 21 r 0 20 r 0 19 r 0 18 r 0 17 r 0 16 r 1 15 reserved r 0 14 r 0 13 r 0 12 r 0 11 r 0 10 r 0 9r0 8r0 7 revision r 0 6r0 5r0 4r0 3r0 2r0 1r0 0r0
agere systems inc. 47 data sheet, rev. 2 fw323 05 october 2001 1394a pci phy/link open host controller interface internal registers (continued) table 35. ohci version register description bit field name type description 31:25 reserved r reserved. bits 31:25 return 0s when read. 24 guid_rom r the fw323 sets this bit if the serial rom is detected. if the serial rom is present, then the bus_info_block and chip configuration data is automatically loaded on hardware reset. 23:16 version r major version of the ohci. the fw323 is compliant with the 1394 open host controller interface specification ; thus, this field reads 01h. 15:8 reserved r reserved. bits 15:8 return 0s when read. 7:0 revision r minor version of the ohci. the fw323 is compliant with the 1394 open host controller interface specification ; thus, this field reads 00h.
48 48 agere systems inc. fw323 05 data sheet, rev. 2 1394a pci phy/link open host controller interface october 2001 internal registers (continued) guid rom register the guid rom register is used to access the serial rom, and is only applicable if bit 24 (guid_rom) in the ohci version register is set. table 36. guid rom register register: guid rom register type: read/set/update offset: 04h default: 00xx 0000h bit field name type de fault 31 addrreset rsu 0 30 reserved r 0 29 r 0 28 r 0 27 r 0 26 r 0 25 rdstart rsu 0 24 reserved r 0 23 rddata ru x 22 ru x 21 ru x 20 ru x 19 ru x 18 ru x 17 ru x 16 ru x 15 reserved r 0 14 r 0 13 r 0 12 r 0 11 r 0 10 r 0 9r0 8r0 7r0 6r0 5r0 4r0 3r0 2r0 1r0 0r0
agere systems inc. 49 data sheet, rev. 2 fw323 05 october 2001 1394a pci phy/link open host controller interface internal registers (continued) table 37. guid rom register description bit field name type description 31 addrreset rsu software sets this bit to reset the guid rom address to 0. when the fw323 completes the reset, it clears this bit. 30:26 reserved r reserved. bits 30:26 return 0s when read. 25 rdstart rsu a read of the currently addressed byte is started when this bit is set. this bit is automatically cleared when the fw323 completes the read of the currently addressed guid rom byte. 24 reserved r reserved. bit 24 returns 0 when read. 23:16 rddata ru this field represents the data read from the guid rom and is only validwhenrdstart=0. 15:0 reserved r reserved. bits 15:0 return 0s when read.
50 50 agere systems inc. fw323 05 data sheet, rev. 2 1394a pci phy/link open host controller interface october 2001 internal registers (continued) asynchronous transmit retries register the asynchronous transmit retries register indicates the number of times the fw323 attempts a retry for asynchronous dma request transmit and for asynchronous physical and dma response transmit. table 38. asynchronous transmit retries register register: asynchronous transmit retries register type: read/write offset: 08h default: 0000 0000h bit field name type default 31 secondlimit r 0 30 r 0 29 r 0 28 cyclelimit r 0 27 r 0 26 r 0 25 r 0 24 r 0 23 r 0 22 r 0 21 r 0 20 r 0 19 r 0 18 r 0 17 r 0 16 r 0 15 reserved r 0 14 r 0 13 r 0 12 r 0 11 maxphysrespretries rw 0 10 rw 0 9rw0 8rw0 7maxatrespretriesrw 0 6rw0 5rw0 4rw0 3 maxatreqretries rw 0 2rw0 1rw0 0rw0
agere systems inc. 51 data sheet, rev. 2 fw323 05 october 2001 1394a pci phy/link open host controller interface internal registers (continued) table 39. asynchronous transmit retries register description bit field name type description 31:29 secondlimit r the second limit field returns 0s when read, since outbound dual- phase retry is not implemented. 28:16 cyclelimit r the cycle limit field returns 0s when read, since outbound dual- phase retry is not implemented. 15:12 reserved r reserved. bits 15:12 return 0s when read. 11:8 maxphysrespretries rw this field tells the physical response unit how many times to attempt to retry the transmit operation for the response packet when a busy acknowledge or ack_data_error is received from the target node. 7:4 maxatrespretries rw this field tells the asynchronous transmit response unit how many times to attempt to retry the transmit operation for the response packet when a busy acknowledge or ack_data_error is received from the target node. 3:0 maxatreqretries rw this field tells the asynchronous transmit dma request unit how many times to attempt to retry the transmit operation for the response packet when a busy acknowledge or ack_data_error is received from the target node.
52 52 agere systems inc. fw323 05 data sheet, rev. 2 1394a pci phy/link open host controller interface october 2001 internal registers (continued) csr data register the csr data register is used to access the bus management csr registers from the host through compare- swap operations. this register contains the data to be stored in a csr if the compare is successful. table 40. csr data register register: csr data register type: read only offset: 0ch default: xxxx xxxxh bit field name type de fault 31 csrdata rwu x 30 rwu x 29 rwu x 28 rwu x 27 rwu x 26 rwu x 25 rwu x 24 rwu x 23 rwu x 22 rwu x 21 rwu x 20 rwu x 19 rwu x 18 rwu x 17 rwu x 16 rwu x 15 rwu x 14 rwu x 13 rwu x 12 rwu x 11 rwu x 10 rwu x 9rwux 8rwux 7rwux 6rwux 5rwux 4rwux 3rwux 2rwux 1rwux 0rwux
agere systems inc. 53 data sheet, rev. 2 fw323 05 october 2001 1394a pci phy/link open host controller interface internal registers (continued) table 41. csr data register description bit field name type description 31:0 csrdata rwu at start of operation, the data to be stored if the compare is successful.
54 54 agere systems inc. fw323 05 data sheet, rev. 2 1394a pci phy/link open host controller interface october 2001 internal registers (continued) csr compare register the csr compare register is used to access the bus management csr registers from the host through compare- swap operations. this register contains the data to be compared with the existing value of the csr resource. table 42. csr compare register register: csr compare register type: read only offset: 10h default: xxxx xxxxh bit field name type de fault 31 csrcompare rw x 30 rw x 29 rw x 28 rw x 27 rw x 26 rw x 25 rw x 24 rw x 23 rw x 22 rw x 21 rw x 20 rw x 19 rw x 18 rw x 17 rw x 16 rw x 15 rw x 14 rw x 13 rw x 12 rw x 11 rw x 10 rw x 9rwx 8rwx 7rwx 6rwx 5rwx 4rwx 3rwx 2rwx 1rwx 0rwx
agere systems inc. 55 data sheet, rev. 2 fw323 05 october 2001 1394a pci phy/link open host controller interface internal registers (continued) table 43. csr compare register description bit field name type description 31:0 csrcompare rw the data to be compared with the existing value of the csr resource.
56 56 agere systems inc. fw323 05 data sheet, rev. 2 1394a pci phy/link open host controller interface october 2001 internal registers (continued) csr control register the csr compare register is used to access the bus management csr registers from the host through compare- swap operations. this register contains the data to be compared with the existing value of the csr resource. table 44. csr control register register: csr control register type: read/write/update offset: 14h default: 8000 000xh bit field name type de fault 31 csrdone ru 1 30 reserved r 0 29 r 0 28 r 0 27 r 0 26 r 0 25 r 0 24 r 0 23 r 0 22 r 0 21 r 0 20 r 0 19 r 0 18 r 0 17 r 0 16 r 0 15 r 0 14 r 0 13 r 0 12 r 0 11 r 0 10 r 0 9r0 8r0 7r0 6r0 5r0 4r0 3r0 2r0 1 csrsel rw x 0rwx
agere systems inc. 57 data sheet, rev. 2 fw323 05 october 2001 1394a pci phy/link open host controller interface internal registers (continued) table 45. csr control register description bit field name type description 31 csrdone ru this bit is set by the fw323 when a compare-swap operation is complete. it is reset whenever this register is written. 30:2 reserved r reserved. bits 30:2 return 0s when read. 1:0 csrsel rw this field selects the csr resource as follows: 00 = bus_manager_id 01 = bandwidth_available 10 = channels_available_hi 11 = channels_available_lo
58 58 agere systems inc. fw323 05 data sheet, rev. 2 1394a pci phy/link open host controller interface october 2001 internal registers (continued) configuration rom header register the configuration rom header register externally maps to the first quadlet of the 1394 configuration rom, offset 48hffff_f000_0400. table 46. configuration rom header register register: configuration rom header register type: read/write offset: 18h default: 0000 0000h bit field name type de fault 31 info_length rw 0 30 rw 0 29 rw 0 28 rw 0 27 rw 0 26 rw 0 25 rw 0 24 rw 0 23 crc_length rw 0 22 rw 0 21 rw 0 20 rw 0 19 rw 0 18 rw 0 17 rw 0 16 rw 0 15 rom_crc_value rw x 14 rw x 13 rw x 12 rw x 11 rw x 10 rw x 9rwx 8rwx 7rwx 6rwx 5rwx 4rwx 3rwx 2rwx 1rwx 0rwx
agere systems inc. 59 data sheet, rev. 2 fw323 05 october 2001 1394a pci phy/link open host controller interface internal registers table 47. configuration rom header register description bit field name type description 31:24 info_length rw ieee 1394 bus management field. must be valid when bit 17 (linkenable) of the host controller control register is set. 23:16 crc_length rw ieee 1394 bus management field. must be valid when bit 17 (linkenable) of the host controller control register is set. 15:0 rom_crc_value rw ieee 1394 bus management field. must be valid at any time bit 17 (linkenable) of the host controller control register is set. if a serial rom is present, then this field is loaded from the serial rom.
60 60 agere systems inc. fw323 05 data sheet, rev. 2 1394a pci phy/link open host controller interface october 2001 internal registers (continued) bus identification register the bus identification register externally maps to the first quadlet in the bus_info_block, 1394 addressable at ffff_f000_0404. table 48. bus identification register register: bus identification register type: read only offset: 1ch default: 3133 3934h bit field name type de fault 31 busid r 0 30 r 0 29 r 1 28 r 1 27 r 0 26 r 0 25 r 0 24 r 1 23 r 0 22 r 0 21 r 1 20 r 1 19 r 0 18 r 0 17 r 1 16 r 1 15 r 0 14 r 0 13 r 1 12 r 1 11 r 1 10 r 0 9r0 8r1 7r0 6r0 5r1 4r1 3r0 2r1 1r0 0r0
agere systems inc. 61 data sheet, rev. 2 fw323 05 october 2001 1394a pci phy/link open host controller interface internal registers (continued) table 49. bus identification register description bit field name type description 310 busid r contains the constant 32h31333934, which is the ascii value for 1394.
62 62 agere systems inc. fw323 05 data sheet, rev. 2 1394a pci phy/link open host controller interface october 2001 internal registers (continued) bus options register the bus options register externally maps to the second quadlet of the bus_info_block, 1394 addressable at ffff_f000_0408. table 50. bus options register register: bus options register type: read/write offset: 20h default: 0000 a002h bit field type default 31 irmc rw x 30 cmc rw x 29 isc rw x 28 bmc rw x 27 pmc rw 0 26 reserved r 0 25 r 0 24 r 0 23 cyc_clk_acc rw x 22 rw x 21 rw x 20 rw x 19 rw x 18 rw x 17 rw x 16 rw x 15 max_rec rw 1 14 rw 0 13 rw 1 12 rw 0 11 reserved r 0 10 r 0 9r0 8r0 7grwx 6rwx 5 reserved r 0 4r0 3r0 2 lnk_spd r 0 1r1 0r0
agere systems inc. 63 data sheet, rev. 2 fw323 05 october 2001 1394a pci phy/link open host controller interface internal registers (continued) table 51. bus options register description bit field name type description 31 irmc rw isochronous resource manager capable. ieee 1394 bus management field. must be valid when bit 17 (linkenable) of the host controller control register is set. 30 cmc rw cycle master capable. ieee 1394 bus management field. must be valid when bit 17 (linkenable) of the host controller control register is set. 29 isc rw isochronous support capable. ieee 1394 bus management field. must be valid when bit 17 (linkenable) of the host controller control register is set. 28 bmc rw bus manager capable. ieee 1394 bus management field. must be valid when bit 17 (linkenable) of the host controller control register is set. 27 pmc rw ieee 1394 bus management field. must be valid when bit 17 (linkenable) of the host controller control register is set. 26:24 reserved r reserved . bits 26:24 return 0s when read. 23:16 cyc_clk_acc rw cycle master clock accuracy. (accuracy in parts per million.) ieee 1394 bus management field. must be valid when bit 17 (linkenable) of the host controller control register is set. 15:12 max_rec rw ieee 1394 bus management field. hardware initializes this field to indicate the maximum number of bytes in a block request packet that is supported by the implementation. this value, max_rec_bytes, must be 512 greater and is calculated by 2 (max_rec + 1) . software may change this field; however, this field must be valid at any time bit 17 (linkenable) of the host controller control register is set. a received block write request packet with a length greater than max_rec_bytes may generate an ack_type_error. this field is not affected by a soft reset, and defaults to value indicating 2048 bytes on a hard reset. 11:8 reserved r reserved. bits 11:8 return 0s when read. 7:6 g rw generation counter. this field is incremented if any portion of the configuration rom has been incremented since the prior bus reset. 5:3 reserved r reserved. bits 5:3 return 0s when read. 2:0 lnk_spd r link speed. this field returns 010, indicating that the link speeds of 100 mbits/s, 200 mbits/s, and 400 mbits/s are supported.
64 64 agere systems inc. fw323 05 data sheet, rev. 2 1394a pci phy/link open host controller interface october 2001 internal registers (continued) guid high register the guid high register represents the upper quadlet in a 64-bit global unique id (guid), which maps to the third quadlet in the bus_info_block 1394 addressable at ffff_f000_0410. this register contains node_vendor_id and chip_id_hi fields. this register initializes to 0s on a hardware reset, which is an illegal guid value. if a serial rom is detected, then the contents of this register are loaded through the serial rom interface after a pci reset. at that point, the contents of this register cannot be changed. if no serial rom is detected, then the contents of this register can be loaded with a pci configuration write to offset 0x80. at that point, the contents of this register cannot be changed. table 52. guid high register bit field name type de fault 31 node_vendor_id r 0 30 r 0 29 r 0 28 r 0 27 r 0 26 r 0 25 r 0 24 r 0 23 r 0 22 r 0 21 r 0 20 r 0 19 r 0 18 r 0 17 r 0 16 r 0 15 r 0 14 r 0 13 r 0 12 r 0 11 r 0 10 r 0 9r0 8r0 7 chip_id_hi r 0 6r0 5r0 4r0 3r0 2r0 1r0 0r0
agere systems inc. 65 data sheet, rev. 2 fw323 05 october 2001 1394a pci phy/link open host controller interface internal registers (continued) register: guid high register type: read only offset: 24h default: 0000 0000h table 53. guid high register description bit field name type description 31:8 node_vendor_id r ieee 1394 bus management fields. 7:0 chip_id_hi r
66 66 agere systems inc. fw323 05 data sheet, rev. 2 1394a pci phy/link open host controller interface october 2001 internal registers (continued) guid low register the guid low register represents the lower quadlet in a 64-bit global unique id (guid), which maps to chip_id_lo in the bus_info_block 1394 addressable at ffff_f000_0414. this register initializes to 0s on a hardware reset and behaves identical to the guid high register. if no serial rom is detected, then the contents of this register can be loaded with a pci configuration write to offset 0x84. table 54. guid low register register: guid low register type: read only offset: 28h default: 0000 0000h bit field name type de fault 31 chip_id_lo r 0 30 r 0 29 r 0 28 r 0 27 r 0 26 r 0 25 r 0 24 r 0 23 r 0 22 r 0 21 r 0 20 r 0 19 r 0 18 r 0 17 r 0 16 r 0 15 r 0 14 r 0 13 r 0 12 r 0 11 r 0 10 r 0 9r0 8r0 7r0 6r0 5r0 4r0 3r0 2r0 1r0 0r0
agere systems inc. 67 data sheet, rev. 2 fw323 05 october 2001 1394a pci phy/link open host controller interface internal registers (continued) table 55. guid low register description bit field name type description 31:0 chip_id_lo r ieee 1394 bus management fields.
68 68 agere systems inc. fw323 05 data sheet, rev. 2 1394a pci phy/link open host controller interface october 2001 internal registers (continued) configuration rom mapping register the configuration rom mapping register contains the start address within system memory that maps to the start address of 1394 configuration rom for this node. table 56. configuration rom mapping register register: configuration rom mapping register type: read/write offset: 34h default: 0000 0000h bit field name type de fault 31 configromaddr rw 0 30 rw 0 29 rw 0 28 rw 0 27 rw 0 26 rw 0 25 rw 0 24 rw 0 23 rw 0 22 rw 0 21 rw 0 20 rw 0 19 rw 0 18 rw 0 17 rw 0 16 rw 0 15 rw 0 14 rw 0 13 rw 0 12 rw 0 11 rw 0 10 rw 0 9 reserved r 0 8r0 7r0 6r0 5r0 4r0 3r0 2r0 1r0 0r0
agere systems inc. 69 data sheet, rev. 2 fw323 05 october 2001 1394a pci phy/link open host controller interface internal registers (continued) table 57. configuration rom mapping register description bit field name type description 31:10 configromaddr rw if a quadlet read request to 1394 offset 48hffff_f000_0400 through offset 48hffff_f000_07ff is received, then the low- order 10 bits of the offset are added to this register to determine the host memory address of the read request. 9:0 reserved r reserved. bits 9:0 return 0s when read.
70 70 agere systems inc. fw323 05 data sheet, rev. 2 1394a pci phy/link open host controller interface october 2001 internal registers (continued) posted write address low register the posted write address low register is used to communicate error information if a write request is posted and an error occurs while writing the posted data packet. table 58. posted write address low register register: posted write address low register type: read/update offset: 38h default: xxxx xxxxh bit field name type de fault 31 offsetlo ru x 30 ru x 29 ru x 28 ru x 27 ru x 26 ru x 25 ru x 24 ru x 23 ru x 22 ru x 21 ru x 20 ru x 19 ru x 18 ru x 17 ru x 16 ru x 15 ru x 14 ru x 13 ru x 12 ru x 11 ru x 10 ru x 9rux 8rux 7rux 6rux 5rux 4rux 3rux 2rux 1rux 0rux
agere systems inc. 71 data sheet, rev. 2 fw323 05 october 2001 1394a pci phy/link open host controller interface internal registers (continued) table 59. posted write address low register description bit field name type description 31:0 offsetlo ru the lower 32 bits of the 1394 destination offset of the write request that failed.
72 72 agere systems inc. fw323 05 data sheet, rev. 2 1394a pci phy/link open host controller interface october 2001 internal registers (continued) posted write address high register the posted write address high register is used to communicate error information if a write request is posted and an error occurs while writing the posted data packet. table 60. posted write address high register register: posted write address high register type: read/update offset: 3ch default: xxxx xxxxh bit field name type de fault 31 sourceid ru x 30 ru x 29 ru x 28 ru x 27 ru x 26 ru x 25 ru x 24 ru x 23 ru x 22 ru x 21 ru x 20 ru x 19 ru x 18 ru x 17 ru x 16 ru x 15 offsethi ru x 14 ru x 13 ru x 12 ru x 11 ru x 10 ru x 9rux 8rux 7rux 6rux 5rux 4rux 3rux 2rux 1rux 0rux
agere systems inc. 73 data sheet, rev. 2 fw323 05 october 2001 1394a pci phy/link open host controller interface internal registers (continued) table 61. posted write address high register description bit field name type description 31:16 sourceid ru this field is the bus and node number of the node that issued the write request that failed. 15:0 offsethi ru the upper 16 bits of the 1394 destination offset of the write request that failed.
74 74 agere systems inc. fw323 05 data sheet, rev. 2 1394a pci phy/link open host controller interface october 2001 internal registers (continued) vendor id register the vendor id register holds the company id of an organization that specifies any vendor-unique registers. table 62. vendor id register register: vendor id register type: read only offset: 40h default: 0000 0000h bit field name type de fault 31 vendorunique r 0 30 r 0 29 r 0 28 r 0 27 r 0 26 r 0 25 r 0 24 r 0 23 r 0 22 r 0 21 r 0 20 r 0 19 r 0 18 r 0 17 r 0 16 r 0 15 vendorcompanyid r 0 14 r 0 13 r 0 12 r 0 11 r 0 10 r 0 9r0 8r0 7r0 6r0 5r0 4r0 3r0 2r0 1r0 0r0
agere systems inc. 75 data sheet, rev. 2 fw323 05 october 2001 1394a pci phy/link open host controller interface internal registers (continued) table 63. vendor id register description bit field name type description 31:24 vendorunique r returns 0 when read, since the fw323 does not specify any vendor unique registers. 23:0 vendorcompanyid r returns 0 when read, since the fw323 does not specify any vendor unique registers.
76 76 agere systems inc. fw323 05 data sheet, rev. 2 1394a pci phy/link open host controller interface october 2001 internal registers (continued) host controller control register the host controller control set/clear register pair provides flags for controlling the ohci portion of the fw323. table 64. host controller control register register: host controller control register type: read/set/clear/update offset: 50h set register 54h clear register default: x00x 0000h bit field name type default 31 reserved r 0 30 nobyteswapdata rsc 0 29 reserved r 0 28 r 0 27 r 0 26 r 0 25 r 0 24 r 0 23 programphyenable rc 0 22 aphyenhancedenable rsc 0 21 reserved r 0 20 r 0 19 lps rs 0 18 postedwriteenable rsc 0 17 linkenable rsu 0 16 softreset rsu 0 15 reserved r 0 14 r 0 13 r 0 12 r 0 11 r 0 10 r 0 9r0 8r0 7r0 6r0 5r0 4r0 3r0 2r0 1r0 0r0
agere systems inc. 77 data sheet, rev. 2 fw323 05 october 2001 1394a pci phy/link open host controller interface internal registers (continued) table 65. host controller control register description bit field name type description 31 reserved r reserved. bit 31 returns 0 when read. 30 nobyteswapdata rsc this bit is used to control byte swapping during host bus accesses involving the data portion of 1394 packets. data is swapped if equal to 0, not swapped when equal to 1. 29:24 reserved r reserved. bits 29:24 return 0s when read. 23 programphyenable rc this bit informs upper-level software that lower-level software has consistently configured the 1394a-2000 enhancements in the link and phy core. when this bit is 1, generic software such as the ohci driver is responsible for configuring 1394a-2000 enhance- ments in the phy core and bit 22 (aphyenhanceenable) in the fw323. when this bit is 0, the generic software may not modify the 1394a-2000 enhancements in the fw323 and cannot interpret the setting of bit 22 (aphyenhanceenable). this bit is initialized from serial eeprom. 22 aphyenhanceenable rsc when bits 23 (programphyenable) and 17 (linkenable) are 1, the ohci driver can set this bit to use all 1394a-2000 enhancements. when bit 23 (programphyenable) is set to 0, the software does not change phy enhancements or this bit. 21:20 reserved r reserved. bits 21:20 return 0s when read. 19 lps rs link power status. this bit drives the lps signal to the phy core within the fw323. 18 postedwriteenable rsc this bit is used to enable (1) or disable (0) posted writes. software should change this bit only when bit 17 (linkenable) is 0. 17 linkenable rsu this bit is cleared to 0 by either a hardware or software reset. soft- ware must set this bit to 1 when the system is ready to begin oper- ation and then force a bus reset. this bit is necessary to keep other nodes from sending transactions before the local system is ready. when this bit is cleared, the fw323 is logically and immedi- ately disconnected from the 1394 bus, no packets are received or processed, nor are packets transmitted. 16 softreset rsu when this bit is set, all fw323 states are reset, all fifos are flushed, and all ohci registers are set to their hardware reset values unless otherwise specified. pci registers are not affected by this bit. this bit remains set while the softreset is in progress and reverts back to 0 when the reset has completed. 15:0 reserved r reserved. bits 15:0 return 0s when read.
78 78 agere systems inc. fw323 05 data sheet, rev. 2 1394a pci phy/link open host controller interface october 2001 internal registers (continued) the self-id buffer pointer register points to the 2 kbyte aligned base address of the buffer in host memory where the self-id packets are stored during bus initialization. bits 31:11 are read/write accessible. table 66. self-id buffer pointer register register: self-id buffer pointer register type: read/write offset: 64h default: xxxx xx00h bit field name type default 31 selfidbufferptr rw x 30 rw x 29 rw x 28 rw x 27 rw x 26 rw x 25 rw x 24 rw x 23 rw x 22 rw x 21 rw x 20 rw x 19 rw x 18 rw x 17 rw x 16 rw x 15 rw x 14 rw x 13 rw x 12 rw x 11 rw x 10 reserved r 0 9r0 8r0 7r0 6r0 5r0 4r0 3r0 2r0 1r0 0r0
agere systems inc. 79 data sheet, rev. 2 fw323 05 october 2001 1394a pci phy/link open host controller interface internal registers (continued) table 67. self-id buffer pointer register description bit field name type description 31:11 selfidbufferptr rw contains the 2 kbyte aligned base address of the buffer in host memory where received self-id packets are stored. 10:0 reserved r reserved.
80 80 agere systems inc. fw323 05 data sheet, rev. 2 1394a pci phy/link open host controller interface october 2001 internal registers (continued) self-id count register the self-id buffer pointer register points to the 2 kbyte aligned base address of the buffer in host memory where the self-id packets are stored during bus initialization. bits 31:11 are read/write accessible. table 68. self-id count register register: self-id count register type: read/write offset: 68h default: x0xx 0000h bit field name type default 31 selfiderror ru x 30 reserved r 0 29 r 0 28 r 0 27 r 0 26 r 0 25 r 0 24 r 0 23 selfidgeneration ru x 22 ru x 21 ru x 20 ru x 19 ru x 18 ru x 17 ru x 16 ru x 15 reserved r 0 14 r 0 13 r 0 12 r 0 11 r 0 10 selfidsize ru 0 9ru0 8ru0 7ru0 6ru0 5ru0 4ru0 3ru0 2ru0 1 reserved r 0 0r0
agere systems inc. 81 data sheet, rev. 2 fw323 05 october 2001 1394a pci phy/link open host controller interface internal registers (continued) table 69. self-id count register description bit field name type description 31 selfiderror ru when this bit is 1, an error was detected during the most recent self-id packet reception. the contents of the self-id buffer are undefined. this bit is cleared after a self-id reception in which no errors are detected. note that an error can be a hardware error or a host bus write error. 30:24 reserved r reserved. bits 30:24 return 0s when read. 23:16 selfidgeneration ru the value in this field increments each time a bus reset is detected. this field rolls over to 0 after reaching 255. 15:11 reserved r reserved. bits 15:11 return 0s when read. 10:2 selfidsize ru this field indicates the number of quadlets that have been written into the self-id buffer for the current bits 23:16 (selfidgeneration field). this includes the header quadlet and the self-id data. this field is cleared to 0 when the self-id reception begins. 1:0 reserved r reserved. bits 1:0 return 0s when read.
82 82 agere systems inc. fw323 05 data sheet, rev. 2 1394a pci phy/link open host controller interface october 2001 internal registers (continued) isochronous receive channel mask high register the isochronous receive channel mask high set/clear register is used to enable packet receives from the upper 32 isochronous data channels. a read from either the set register or clear register returns the content of the isochronous receive channel mask high register. table 70. isochronous receive channel mask high register register: isochronous receive channel mask high register type: read/set/clear offset: 70h set register 74h clear register default: xxxx xxxxh bit field name type default 31 isochannel63 rsc x 30 isochannel62 rsc x 29 isochannel61 rsc x 28 isochannel60 rsc x 27 isochannel59 rsc x 26 isochannel58 rsc x 25 isochannel57 rsc x 24 isochannel56 rsc x 23 isochannel55 rsc x 22 isochannel54 rsc x 21 isochannel53 rsc x 20 isochannel52 rsc x 19 isochannel51 rsc x 18 isochannel50 rsc x 17 isochannel49 rsc x 16 isochannel48 rsc x 15 isochannel47 rsc x 14 isochannel46 rsc x 13 isochannel45 rsc x 12 isochannel44 rsc x 11 isochannel43 rsc x 10 isochanne42l rsc x 9 isochannel41 rsc x 8 isochannel40 rsc x 7 isochannel39 rsc x 6 isochannel38 rsc x 5 isochannel37 rsc x 4 isochannel36 rsc x 3 isochannel35 rsc x 2 isochannel34 rsc x 1 isochannel33 rsc x 0 isochannel32 rsc x
agere systems inc. 83 data sheet, rev. 2 fw323 05 october 2001 1394a pci phy/link open host controller interface internal registers (continued) table 71. isochronous receive channel mask high register description bit field name type description 31 isochannel63 rsc if bit 31 is set, iso channel number 63 is enabled. 30 isochannel62 rsc if bit 30 is set, iso channel number 62 is enabled. 29 isochannel61 rsc if bit 29 is set, iso channel number 61 is enabled. 28 isochannel60 rsc if bit 28 is set, iso channel number 60 is enabled. 27 isochannel59 rsc if bit 27 is set, iso channel number 59 is enabled. 26 isochannel58 rsc if bit 26 is set, iso channel number 58 is enabled. 25 isochannel57 rsc if bit 25 is set, iso channel number 57 is enabled. 24 isochannel56 rsc if bit 24 is set, iso channel number 56 is enabled. 23 isochannel55 rsc if bit 23 is set, iso channel number 55 is enabled. 22 isochannel54 rsc if bit 22 is set, iso channel number 54 is enabled. 21 isochannel53 rsc if bit 21 is set, iso channel number 53 is enabled. 20 isochannel52 rsc if bit 20 is set, iso channel number 52 is enabled. 19 isochannel51 rsc if bit 19 is set, iso channel number 51 is enabled. 18 isochannel50 rsc if bit 18 is set, iso channel number 50 is enabled. 17 isochannel49 rsc if bit 17 is set, iso channel number 49 is enabled. 16 isochannel48 rsc if bit 16 is set, iso channel number 48 is enabled. 15 isochannel47 rsc if bit 15 is set, iso channel number 47 is enabled. 14 isochannel46 rsc if bit 14 is set, iso channel number 46 is enabled. 13 isochannel45 rsc if bit 13 is set, iso channel number 45 is enabled. 12 isochannel44 rsc if bit 12 is set, iso channel number 44 is enabled. 11 isochannel43 rsc if bit 11 is set, iso channel number 43 is enabled. 10 isochannel42 rsc if bit 10 is set, iso channel number 42 is enabled. 9 isochannel41 rsc if bit 9 is set, iso channel number 41 is enabled. 8 isochannel40 rsc if bit 8 is set, iso channel number 40 is enabled. 7 isochannel39 rsc if bit 7 is set, iso channel number 39 is enabled. 6 isochannel38 rsc if bit 6 is set, iso channel number 38 is enabled. 5 isochannel37 rsc if bit 5 is set, iso channel number 37 is enabled. 4 isochannel36 rsc if bit 4 is set, iso channel number 36 is enabled. 3 isochannel35 rsc if bit 3 is set, iso channel number 35 is enabled. 2 isochannel34 rsc if bit 2 is set, iso channel number 34 is enabled. 1 isochannel33 rsc if bit 1 is set, iso channel number 33 is enabled. 0 isochannel32 rsc if bit 0 is set, iso channel number 32 is enabled.
84 84 agere systems inc. fw323 05 data sheet, rev. 2 1394a pci phy/link open host controller interface october 2001 internal registers (continued) isochronous receive channel mask low register the isochronous receive channel mask low set/clear register is used to enable packet receives from the lower 32 isochronous data channels. table 72. isochronous receive channel mask low register register: isochronous receive channel mask low register type: read/set/clear offset: 78h set register 7ch clear register default: xxxx xxxxh bit field name type default 31 isochannel31 rsc x 30 isochannel30 rsc x 29 isochannel29 rsc x 28 isochannel28 rsc x 27 isochannel27 rsc x 26 isochannel26 rsc x 25 isochannel25 rsc x 24 isochannel24 rsc x 23 isochannel23 rsc x 22 isochannel22 rsc x 21 isochannel21 rsc x 20 isochannel20 rsc x 19 isochannel19 rsc x 18 isochannel18 rsc x 17 isochannel17 rsc x 16 isochannel16 rsc x 15 isochannel15 rsc x 14 isochannel14 rsc x 13 isochannel13 rsc x 12 isochannel12 rsc x 11 isochannel11 rsc x 10 isochannel10 rsc x 9 isochannel9 rsc x 8 isochannel8 rsc x 7 isochannel7 rsc x 6 isochannel6 rsc x 5 isochannel5 rsc x 4 isochannel4 rsc x 3 isochannel3 rsc x 2 isochannel2 rsc x 1 isochannel1 rsc x 0 isochannel0 rsc x
agere systems inc. 85 data sheet, rev. 2 fw323 05 october 2001 1394a pci phy/link open host controller interface internal registers (continued) table 73. isochronous receive channel mask low register description bit field name type description 31 isochannel31 rsc if bit 31 is set, iso channel number 31 is enabled. 30 isochannel30 rsc if bit 30 is set, iso channel number 30 is enabled. 29 isochannel29 rsc if bit 29 is set, iso channel number 29 is enabled. 28 isochannel28 rsc if bit 28 is set, iso channel number 28 is enabled. 27 isochannel27 rsc if bit 27 is set, iso channel number 27 is enabled. 26 isochannel26 rsc if bit 26 is set, iso channel number 26 is enabled. 25 isochannel25 rsc if bit 25 is set, iso channel number 25 is enabled. 24 isochannel24 rsc if bit 24 is set, iso channel number 24 is enabled. 23 isochannel23 rsc if bit 23 is set, iso channel number 23 is enabled. 22 isochannel22 rsc if bit 22 is set, iso channel number 22 is enabled. 21 isochannel21 rsc if bit 21 is set, iso channel number 21 is enabled. 20 isochannel20 rsc if bit 20 is set, iso channel number 20 is enabled. 19 isochannel19 rsc if bit 19 is set, iso channel number 19 is enabled. 18 isochannel18 rsc if bit 18 is set, iso channel number 18 is enabled. 17 isochannel17 rsc if bit 17 is set, iso channel number 17 is enabled. 16 isochannel16 rsc if bit 16 is set, iso channel number 16 is enabled. 15 isochannel15 rsc if bit 15 is set, iso channel number 15 is enabled. 14 isochannel14 rsc if bit 14 is set, iso channel number 14 is enabled. 13 isochannel13 rsc if bit 13 is set, iso channel number 13 is enabled. 12 isochannel12 rsc if bit 12 is set, iso channel number 12 is enabled. 11 isochannel11 rsc if bit 11 is set, iso channel number 11 is enabled. 10 isochannel10 rsc if bit 10 is set, iso channel number 10 is enabled. 9 isochannel9 rsc if bit 9 is set, iso channel number 9 is enabled. 8 isochannel8 rsc if bit 8 is set, iso channel number 8 is enabled. 7 isochannel7 rsc if bit 7 is set, iso channel number 7 is enabled. 6 isochannel6 rsc if bit 6 is set, iso channel number 6 is enabled. 5 isochannel5 rsc if bit 5 is set, iso channel number 5 is enabled. 4 isochannel4 rsc if bit 4 is set, iso channel number 4 is enabled. 3 isochannel3 rsc if bit 3 is set, iso channel number 3 is enabled. 2 isochannel2 rsc if bit 2 is set, iso channel number 2 is enabled. 1 isochannel1 rsc if bit 1 is set, iso channel number 1 is enabled. 0 isochannel0 rsc if bit 0 is set, iso channel number 0 is enabled.
86 86 agere systems inc. fw323 05 data sheet, rev. 2 1394a pci phy/link open host controller interface october 2001 internal registers (continued) interrupt event register the interrupt event set/clear register reflects the state of the various fw323 interrupt sources. the interrupt bits are set by an asserting edge of the corresponding interrupt signal or by writing a 1 in the corresponding bit in the set register. the only mechanism to clear the bits in this register is to write a 1 to the corresponding bit in the clear register. this register is fully compliant with ohci and the fw323 adds ohci 1.0 compliant vendor-specific interrupt function to bit 30. when reading the interrupt event register, the return value is the bit-wise and function of the interrupt event and interrupt mask registers per the 1394 open host controller interface specification . table 74. interrupt event register bit field name type default 31 reserved r 0 30 vendorspecific rsc x 29 reserved r 0 28 r 0 27 r 0 26 phyregrcvd rscu x 25 cycletoollong rscu x 24 unrecoverableerror rscu x 23 cycleinconsistent rscu x 22 cyclelost rscu x 21 cycle64seconds rscu x 20 cyclesynch rscu x 19 phy rscu x 18 reserved r 0 17 busreset rscu x 16 selfidcomplete rscu x 15 reserved r 0 14 r 0 13 r 0 12 r 0 11 r 0 10 r 0 9 lockresperr rscu x 8 postedwriteerr rscu x 7 isochrx ru x 6 isochtx ru x 5 rspkt rscu x 4 rqpkt rscu x 3 arrs rscu x 2arrqrscux 1 resptxcomplete rscu x 0 reqtxcomplete rscu x
agere systems inc. 87 data sheet, rev. 2 fw323 05 october 2001 1394a pci phy/link open host controller interface internal registers (continued) register: interrupt event register type: read/set/clear/update offset: 80h set register 84h clear register (returns the content of the interrupt event and interrupt mask registers when read) default: xxxx 0xxxh table 75. interrupt event register description bit field name type description 31 reserved r reserved. bit 31 returns 0 when read. 30 vendorspecific rsc this vendor-specific interrupt event is reported when serial rom read is complete. 29:27 reserved r reserved. bits 29:27 return 0s when read. 26 phyregrcvd rscu the fw323 has received a phy core register data byte which can be read from the phy core layer control register. 25 cycletoolong rscu if bit 21 (cyclemaster) of the link control register is set, then this indicates that over 125 ms have elapsed between the start of sending a cycle start packet and the end of a subaction gap. the link control register bit 21 (cyclemaster) is cleared by this event. 24 unrecoverableerror rscu this event occurs when the fw323 encounters any error that forces it to stop operations on any or all of its subunits, for example, when a dma context sets its dead bit. while this bit is set, all normal interrupts for the context(s) that caused this inter- rupt are blocked from being set. 23 cycleinconsistent rscu a cycle start was received that had values for cycleseconds and cyclecount fields that are different from the values in bits 31:25 (cycleseconds field) and bits 24:12 (cyclecount field) of the isoch- ronous cycle timer register. 22 cyclelost rscu a lost cycle is indicated when no cycle_start packet is sent/ received between two successive cyclesynch events. a lost cycle can be predicted when a cycle_start packet does not immediately follow the first subaction gap after the cyclesynch event or if an arbitration reset gap is detected after a cyclesynch event without an intervening cycle start. this bit may be set either when it occurs or when logic predicts that it will occur. 21 cycle64seconds rscu indicates that the seventh bit of the cycle second counter has changed. 20 cyclesynch rscu indicates that a new isochronous cycle has started. this bit is set when the low order bit of the cycle count toggles. 19 phy rscu indicates the phy core requests an interrupt through a status transfer. 18 reserved r reserved. bit 18 returns 0 when read. 17 busreset rscu indicates that the phy core chip has entered bus reset mode. 16 selfidcomplete rscu a selfid packet stream has been received. it is generated at the end of the bus initialization process. this bit is turned off simul- taneously when bit 17 (busreset) is turned on.
88 88 agere systems inc. fw323 05 data sheet, rev. 2 1394a pci phy/link open host controller interface october 2001 internal registers (continued) table 75. interrupt event register description (continued) bit field name type description 15:10 reserved ru reserved. bits 15:10 return 0s when read. 9 lockresperr ru indicates that the fw323 sent a lock response for a lock request to a serial bus register, but did not receive an ack_complete. 8 postedwriteerr rscu indicates that a host bus error occurred while the fw323 was trying to write a 1394 write request, which had already been given an ack_complete, into system memory. 7 isochrx rscu isochronous receive dma interrupt. indicates that one or more isochronous receive contexts have generated an interrupt. this is not a latched event; it is the oring of all bits in the isochronous receive interrupt event and isochronous receive interrupt mask registers. the isochronous receive interrupt event register indi- cates which contexts have interrupted. 6 isochtx rscu isochronous transmit dma interrupt. indicates that one or more isochronous transmit contexts have generated an interrupt. this is not a latched event; it is the oring of all bits in the isochro- nous transmit interrupt event and isochronous transmit interrupt mask registers. the isochronous transmit interrupt event register indicates which contexts have interrupted. 5 rspkt rscu indicates that a packet was sent to an asynchronous receive response context buffer and the descriptors xferstatus and rescount fields have been updated. 4 rqpkt rscu indicates that a packet was sent to an asynchronous receive request context buffer and the descriptors xferstatus and rescount fields have been updated. 3arrsrscu asynchronous receive response dma interrupt. this bit is conditionally set upon completion of an arrs dma context command descriptor. 2 arrq rscu asynchronous receive request dma interrupt. this bit is conditionally set upon completion of an arrq dma context command descriptor. 1 resptxcomplete rscu asynchronous response transmit dma interrupt. this bit is conditionally set upon completion of an atrs dma command. 0 reqtxcomplete rscu asynchronous request transmit dma interrupt. this bit is conditionally set upon completion of an atrq dma command.
agere systems inc. 89 data sheet, rev. 2 fw323 05 october 2001 1394a pci phy/link open host controller interface internal registers (continued) interrupt mask register the interrupt mask set/clear register is used to enable the various fw323 interrupt sources. reads from either the set register or the clear register always return the contents of the interrupt mask register. in all cases except masterintenable (bit 31), the enables for each interrupt event align with the interrupt event register bits (see tables 74 and 75). this register is fully compliant with ohci and the fw323 adds an ohci 1.0 compliant interrupt function to bit 30. table 76. interrupt mask register register: interrupt mask register type: read/set/clear/update offset: 88h set register 8ch clear register default: xxxx 0xxxh bit field name type default 31 masterintenable r 0 30 vendorspecific rsc x 29 reserved r 0 28 r 0 27 r 0 26 phyregrcvd rscu x 25 cycletoollong rscu x 24 unrecoverableerror rscu x 23 cycleinconsistent rscu x 22 cyclelost rscu x 21 cycle64seconds rscu x 20 cyclesynch rscu x 19 phy core rscu x 18 reserved r 0 17 busreset rscu x 16 selfidcomplete rscu x 15 reserved r 0 14 r 0 13 r 0 12 r 0 11 r 0 10 r 0 9 lockresperr rscu x 8 postedwriteerr rscu x 7 isochrx ru x 6 isochtx ru x 5 rspkt rscu x 4 rqpkt rscu x 3 arrs rscu x 2arrqrscux 1 resptxcomplete rscu x 0 reqtxcomplete rscu x
90 90 agere systems inc. fw323 05 data sheet, rev. 2 1394a pci phy/link open host controller interface october 2001 internal registers (continued) table 77. interrupt mask register description bit field name type description 31 masterintenable rscu master interrupt enable. if this bit is set, then external interrupts are generated in accordance with the interrupt mask register. if this bit is cleared, then external interrupts are not generated, regard- less of the interrupt mask register settings. 30 vendorspecific rsc when this bit is set, this vendor-specific interrupt mask enables interrupt generation when bit 30 (vendorspecific) of the interrupt event register is set. 29:0 same as table 74, interrupt event register.
agere systems inc. 91 data sheet, rev. 2 fw323 05 october 2001 1394a pci phy/link open host controller interface internal registers (continued) isochronous transmit interrupt event register the isochronous transmit interrupt event set/clear register reflects the interrupt state of the isochronous transmit contexts. an interrupt is generated on behalf of an isochronous transmit context if an output_last command completes and its interrupt bits are set. upon determining that the interrupt event register isochtx (bit 6) interrupt has occurred, software can check this register to determine which context(s) caused the interrupt. the interrupt bits are set by an asserting edge of the corresponding interrupt signal, or by writing a 1 in the corresponding bit in the set register. the only mechanism to clear the bits in this register is to write a 1 to the corresponding bit in the clear register. table 78. isochronous transmit interrupt event register bit field name type defa ult 31 reserved r 0 30 r 0 29 r 0 28 r 0 27 r 0 26 r 0 25 r 0 24 r 0 23 r 0 22 r 0 21 r 0 20 r 0 19 r 0 18 r 0 17 r 0 16 r 0 15 r 0 14 r 0 13 r 0 12 r 0 11 r 0 10 r 0 9r0 8r0 7 isoxmit7 rscu x 6 isoxmit6 rscu x 5 isoxmit5 rscu x 4 isoxmit4 rscu x 3 isoxmit3 rscu x 2 isoxmit2 rscu x 1 isoxmi1t rscu x 0 isoxmit0 rscu x
92 92 agere systems inc. fw323 05 data sheet, rev. 2 1394a pci phy/link open host controller interface october 2001 internal registers (continued) register: isochronous transmit interrupt event register type: read/set/clear offset: 90h set register 94h clear register (returns isoxmitevent and isoxmitmask when read) default: 0000 00xxh table 79. isochronous transmit interrupt event register description bit field name type description 31:8 reserved r reserved. bits 31:8 return 0s when read. 7 isoxmit7 rscu isochronous transmit channel 7 caused the interrupt event register bit 6 (isochtx) interrupt. 6 isoxmit6 rscu isochronous transmit channel 6 caused the interrupt event register bit 6 (isochtx) interrupt. 5 isoxmit5 rscu isochronous transmit channel 5 caused the interrupt event register bit 6 (isochtx) interrupt. 4 isoxmit4 rscu isochronous transmit channel 4 caused the interrupt event register bit 6 (isochtx) interrupt. 3 isoxmit3 rscu isochronous transmit channel 3 caused the interrupt event register bit 6 (isochtx) interrupt. 2 isoxmit2 rscu isochronous transmit channel 2 caused the interrupt event register bit 6 (isochtx) interrupt. 1 isoxmit1 rscu isochronous transmit channel 1 caused the interrupt event register bit 6 (isochtx) interrupt. 0 isoxmit0 rscu isochronous transmit channel 0 caused the interrupt event register bit 6 (isochtx) interrupt.
agere systems inc. 93 data sheet, rev. 2 fw323 05 october 2001 1394a pci phy/link open host controller interface internal registers (continued) isochronous transmit interrupt mask register the isochronous transmit interrupt mask set/clear register is used to enable the isochtx interrupt source on a per- channel basis. reads from either the set register or the clear register always return the contents of the isochronous transmit interrupt mask register. in all cases, the enables for each interrupt event align with the event register bits detailed in table 81 and table 82. table 80. isochronous transmit interrupt mask register register: isochronous transmit interrupt mask register type: read/set/clear offset: 98h set register 9ch clear register (returns isoxmitevent and isoxmitmask when read) default: 0000 00xxh bit field name type default 31 reserved r 0 30 r 0 29 r 0 28 r 0 27 r 0 26 r 0 25 r 0 24 r 0 23 r 0 22 r 0 21 r 0 20 r 0 19 r 0 18 r 0 17 r 0 16 r 0 15 r 0 14 r 0 13 r 0 12 r 0 11 r 0 10 r 0 9r0 8r0 7 isoxmit7 rsc x 6 isoxmit6 rsc x 5 isoxmit5 rsc x 4 isoxmit4 rsc x 3 isoxmit3 rsc x 2 isoxmit2 rsc x 1 isoxmi1t rsc x 0 isoxmit0 rsc x
94 94 agere systems inc. fw323 05 data sheet, rev. 2 1394a pci phy/link open host controller interface october 2001 internal registers (continued) isochronous receive interrupt event register the isochronous receive interrupt event set/clear register reflects the interrupt state of the isochronous receive contexts. an interrupt is generated on behalf of an isochronous receive context if an input_* command completes and its interrupt bits are set. upon determining that the interrupt event register isochrx (bit 7) interrupt has occurred, software can check this register to determine which context(s) caused the interrupt. the interrupt bits are set by an asserting edge of the corresponding interrupt signal, or by writing a 1 in the corresponding bit in the set register. the only mechanism to clear the bits in this register is to write a 1 to the corresponding bit in the clear register table 81. isochronous receive interrupt event register bit field name type default 31 reserved r 0 30 r 0 29 r 0 28 r 0 27 r 0 26 r 0 25 r 0 24 r 0 23 r 0 22 r 0 21 r 0 20 r 0 19 r 0 18 r 0 17 r 0 16 r 0 15 r 0 14 r 0 13 r 0 12 r 0 11 r 0 10 r 0 9r0 8r0 7 isorecv7 rscu 0 6 isorecv6 rscu 0 5 isorecv5 rscu 0 4 isorecv4 rscu 0 3 isorecv3 rscu 0 2 isorecv2 rscu 0 1 isorecv1 rscu 0 0 isorecv0 rscu 0
agere systems inc. 95 data sheet, rev. 2 fw323 05 october 2001 1394a pci phy/link open host controller interface internal registers (continued) register: isochronous receive interrupt event register type: read/set/clear/update offset: a0h set register a4h clear register default: 0000 0000h table 82. isochronous receive interrupt event description bit field name type description 31:8 reserved r reserved. bits 31:8 return 0s when read. 7 isorecv7 rscu isochronous receive context 7 caused the interrupt event register bit 7 (isochrx) interrupt. 6 isorecv6 rscu isochronous receive context 6 caused the interrupt event register bit 7 (isochrx) interrupt. 5 isorecv5 rscu isochronous receive context 5 caused the interrupt event register bit 7 (isochrx) interrupt. 4 isorecv4 rscu isochronous receive context 4 caused the interrupt event register bit 7 (isochrx) interrupt. 3 isorecv3 rscu isochronous receive context 3 caused the interrupt event register bit 7 (isochrx) interrupt. 2 isorecv2 rscu isochronous receive context 2 caused the interrupt event register bit 7 (isochrx) interrupt. 1 isorecv1 rscu isochronous receive context 1 caused the interrupt event register bit 7 (isochrx) interrupt. 0 isorecv0 rscu isochronous receive context 0 caused the interrupt event register bit 7 (isochrx) interrupt.
96 96 agere systems inc. fw323 05 data sheet, rev. 2 1394a pci phy/link open host controller interface october 2001 internal registers (continued) isochronous receive interrupt mask register the isochronous receive interrupt mask set/clear register is used to enable the isochrx interrupt source on a per- channel basis. reads from either the set register or the clear register always return the contents of the isochronous transmit interrupt mask register. in all cases, the enables for each interrupt event align with the event register bits. table 83. isochronous receive interrupt mask register register: isochronous receive interrupt mask register type: read/set/clear offset: a8h set register ach clear register default: 0000 000xh bit field name type default 31 reserved r 0 30 r 0 29 r 0 28 r 0 27 r 0 26 r 0 25 r 0 24 r 0 23 r 0 22 r 0 21 r 0 20 r 0 19 r 0 18 r 0 17 r 0 16 r 0 15 r 0 14 r 0 13 r 0 12 r 0 11 r 0 10 r 0 9r0 8r0 7 isorecv7 rsc 0 6 isorecv6 rsc 0 5 isorecv5 rsc 0 4 isorecv4 rsc 0 3 isorecv3 rsc 0 2 isorecv2 rsc 0 1 isorecv1 rsc 0 0 isorecv0 rsc 0
agere systems inc. 97 data sheet, rev. 2 fw323 05 october 2001 1394a pci phy/link open host controller interface internal registers (continued) fairness control register the fairness control register provides a mechanism by which software can direct the host controller to transmit multiple asynchronous requests during a fairness interval. table 84. fairness control register register: fairness control register type: read only offset: dch default: 0000 0000h bit field name type defa ult 31 reserved r 0 30 r 0 29 r 0 28 r 0 27 r 0 26 r 0 25 r 0 24 r 0 23 r 0 22 r 0 21 r 0 20 r 0 19 r 0 18 r 0 17 r 0 16 r 0 15 r 0 14 r 0 13 r 0 12 r 0 11 r 0 10 r 0 9r0 8r0 7pri_reqrw 0 6rw0 5rw0 4rw0 3rw0 2rw0 1rw0 0rw0
98 98 agere systems inc. fw323 05 data sheet, rev. 2 1394a pci phy/link open host controller interface october 2001 internal registers (continued) table 85. fairness control register description bit field name type description 31:8 reserved r reserved. bits 31:8 return 0s when read. 7:0 pri_req rw this field specifies the maximum number of priority arbitration requests for asyn- chronous request packets that the link is permitted to make of the phy core during fairness interval.
agere systems inc. 99 data sheet, rev. 2 fw323 05 october 2001 1394a pci phy/link open host controller interface internal registers (continued) link control register the link control register provides flags to enable and configure the link core cycle timer and receiver portions of the fw323. table 86. link control register register: link control register type: read/set/clear/update offset: e0h set register e4h clear register default: 00x0 0x00h bit field name type defa ult 31 reserved r 0 30 r 0 29 r 0 28 r 0 27 r 0 26 r 0 25 r 0 24 r 0 23 r 0 22 cyclesource r 0 21 cyclemaster r 0 20 cycletimerenable r 0 19 reserved r 0 18 r 0 17 r 0 16 r 0 15 r 0 14 r 0 13 r 0 12 r 0 11 r 0 10 rcvphypkt r 0 9 rcvselfid r 0 8 reserved r 0 7r0 6r0 5r0 4r0 3r0 2r0 1r0 0r0
100 100 agere systems inc. fw323 05 data sheet, rev. 2 1394a pci phy/link open host controller interface october 2001 internal registers (continued) table 87. link control register description bit field name type description 31:23 reserved r reserved. bits 31:23 return 0s when read. 22 cyclesource rsc set to 0, since the fw323 does not support an external cycle timer. 21 cyclemaster rscu when this bit is set, and the phy core has notified the fw323 that it is root, the fw323 generates a cycle start packet every time the cycle timer rolls over, based on the setting of bit 22. when this bit is cleared, the ohci accepts received cycle start packets to main- tain synchronization with the node which is sending them. this bit is automatically reset when bit 25 (cycletoolong) of the interrupt event register is set and cannot be set until bit 25 (cycletoolong) is cleared. 20 cycletimerenable rsc when this bit is set, the cycle timer offset counts cycles of the 24.576 mhz clock and rolls over at the appropriate time based on the settings of the above bits. when this bit is cleared, the cycle timer offset does not count. 19:11 reserved r reserved. bits 19:11 return 0s when read. 10 rcvphypkt rsc when this bit is set, the receiver accepts incoming phy core packets into the ar request context if the ar request context is enabled. this does not control receipt of self-identification. 9 rcvselfid rsc when this bit is set, the receiver accepts incoming self-identifica- tion packets. before setting this bit to 1, software must ensure that the self-id buffer pointer register contains a valid address. 8:0 reserved r reserved. bits 8:0 return 0s when read.
agere systems inc. 101 data sheet, rev. 2 fw323 05 october 2001 1394a pci phy/link open host controller interface internal registers (continued) node identification register the node identification register contains the address of the node on which the ohci resides, and indicates the valid node number status. the 16-bit combination of the busnumber field (bits 15:6) and the nodenumber field (bits 5:0) is referred to as the node id. table 88. node identification register register: node identification register type: read/write/update offset: e8h default: 0000 ffxxh bit field name type defa ult 31 idvalid ru 0 30 root ru 0 29 reserved r 0 28 r 0 27 cps ru 0 26 reserved r 0 25 r 0 24 r 0 23 r 0 22 r 0 21 r 0 20 r 0 19 r 0 18 r 0 17 r 0 16 r 0 15 busnumber rwu 1 14 rwu 1 13 rwu 1 12 rwu 1 11 rwu 1 10 rwu 1 9rwu1 8rwu1 7rwu1 6rwu1 5 nodenumber ru 0 4ru0 3ru0 2ru0 1ru0 0ru0
102 102 agere systems inc. fw323 05 data sheet, rev. 2 1394a pci phy/link open host controller interface october 2001 internal registers (continued) table 89. node identification register description bit field name type description 31 idvalid ru this bit indicates whether or not the fw323 has a valid node number. it is cleared when a 1394 bus reset is detected and set when the fw323 receives a new node number from the phy core. 30 root ru this bit is set during the bus reset process if the attached phy core is root. 29:28 reserved r reserved. bits 29:28 return 0s when read. 27 cps ru set if the phy core is reporting that cable power status is ok. 26:16 reserved r reserved. bits 26:16 return 0s when read. 15:6 busnumber rwu this number is used to identify the specific 1394 bus to which the fw323 belongs when multiple 1394-compatible buses are connected via a bridge. 5:0 nodenumber ru this number is the physical node number established by the phy core during self-identification. it is automatically set to the value received from the phy core after the self-identification phase. if the phy core sets the nodenumber to 63, then software should not set contextcontrol.run for either of the at dma contexts.
agere systems inc. 103 data sheet, rev. 2 fw323 05 october 2001 1394a pci phy/link open host controller interface internal registers (continued) phy core layer control register the phy core layer control register is used to read or write a phy core register. table 90. phy core layer control register register: phy core layer control register type: read/write/update offset: ech default: 0000 0000h bit field name type defa ult 31 rddone ru 0 30 reserved r 0 29 r 0 28 r 0 27 rdaddr ru 0 26 ru 0 25 ru 0 24 ru 0 23 rddata ru 0 22 ru 0 21 ru 0 20 ru 0 19 ru 0 18 ru 0 17 ru 0 16 ru 0 15 rdreg rwu 0 14 wrreg rwu 0 13 reserved r 0 12 r 0 11 regaddr rw 0 10 rw 0 9rw0 8rw0 7wrdatarw 0 6rw0 5rw0 4rw0 3rw0 2rw0 1rw0 0rw0
104 104 agere systems inc. fw323 05 data sheet, rev. 2 1394a pci phy/link open host controller interface october 2001 internal registers (continued) table 91. phy core layer control register description bit field name type description 31 rddone ru this bit is cleared to 0 by the fw323 when either bit 15 (rdreg) or bit 14 (wrreg) is set. this bit is set when a register transfer is received from the phy core. 30:28 reserved r reserved. bits 30:28 return 0s when read. 27:24 rdaddr ru this is the address of the register most recently received from the phy core. 23:16 rddata ru this field is the contents of a phy core register which has been read. 15 rdreg rwu this bit is set by software to initiate a read request to a phy core register and is cleared by hardware when the request has been sent. bit 14 (wrreg) and bit 15 (rdreg) must be used exclusively. 14 wrreg rwu this bit is set by software to initiate a write request to a phy core register and is cleared by hardware when the request has been sent. bit 14 (wrreg) and bit 15 (rdreg) must be used exclusively. 13:12 reserved r reserved. bits 13:12 return 0s when read. 11:8 regaddr rw this field is the address of the phy core register to be written or read. 7:0 wrdata rw this field is the data to be written to a phy core register and is ignored for reads.
agere systems inc. 105 data sheet, rev. 2 fw323 05 october 2001 1394a pci phy/link open host controller interface internal registers (continued) isochronous cycle timer register the isochronous cycle timer register indicates the current cycle number and offset. when the fw323 is cycle master, this register is transmitted with the cycle start message. when the fw323 is not cycle master, this register is loaded with the data field in an incoming cycle start. in the event that the cycle start message is not received, the fields can continue incrementing on their own (if programmed) to maintain a local time reference. table 92. isochronous cycle timer register bit field name type defa ult 31 cycleseconds rwu 0 30 rwu 0 29 rwu 0 28 rwu 0 27 rwu 0 26 rwu 0 25 rwu 0 24 cyclecount rwu 0 23 rwu 0 22 rwu 0 21 rwu 0 20 rwu 0 19 rwu 0 18 rwu 0 17 rwu 0 16 rwu 0 15 rwu 0 14 rwu 0 13 rwu 0 12 rwu 0 11 cycleoffset rwu 0 10 rwu 0 9rwu0 8rwu0 7rwu0 6rwu0 5rwu0 4rwu0 3rwu0 2rwu0 1rwu0 0rwu0
106 106 agere systems inc. fw323 05 data sheet, rev. 2 1394a pci phy/link open host controller interface october 2001 internal registers (continued) register: isochronous cycle timer register type: read/write/update offset: f0h default: xxxx xxxxh table 93. isochronous cycle timer register description bit field name type description 31:25 cycleseconds rwu this field counts seconds [rollovers from bits 24:12 (cyclecount field)] modulo 128. 24:12 cyclecount rwu this field counts cycles [rollovers from bits 11:0 (cycleoffset field)] modulo 8000. 11:0 cycleoffset rwu this field counts 24.576 mhz clocks modulo 3072, i.e., 125 ms. if an external 8 khz clock configuration is being used, then this bit must be set to 0 at each tick of the external clock.
agere systems inc. 107 data sheet, rev. 2 fw323 05 october 2001 1394a pci phy/link open host controller interface internal registers (continued) asynchronous request filter high register the asynchronous request filter high set/clear register is used to enable asynchronous receive requests on a per- node basis, and handles the upper node ids. when a packet is destined for either the physical request context or the arrq context, the source node id is examined. if the bit corresponding to the node id is not set in this register, then the packet is not acknowledged and the request is not queued. the node id comparison is done if the source node is on the same bus as the fw323. all nonlocal bus sourced packets are not acknowledged unless bit 31 in this register is set. table 94. asychronous request filter high register bit field name type defa ult 31 asynreqallbuses rsc 0 30 asynreqresource62 rsc 0 29 asynreqresource61 rsc 0 28 asynreqresource60 rsc 0 27 asynreqresource59 rsc 0 26 asynreqresource58 rsc 0 25 asynreqresource57 rsc 0 24 asynreqresource56 rsc 0 23 asynreqresource55 rsc 0 22 asynreqresource54 rsc 0 21 asynreqresource53 rsc 0 20 asynreqresource52 rsc 0 19 asynreqresource51 rsc 0 18 asynreqresource50 rsc 0 17 asynreqresource49 rsc 0 16 asynreqresource48 rsc 0 15 asynreqresource47 rsc 0 14 asynreqresource46 rsc 0 13 asynreqresource45 rsc 0 12 asynreqresource44 rsc 0 11 asynreqresource43 rsc 0 10 asynreqresource42 rsc 0 9 asynreqresource41 rsc 0 8 asynreqresource40 rsc 0 7 asynreqresource39 rsc 0 6 asynreqresource38 rsc 0 5 asynreqresource37 rsc 0 4 asynreqresource36 rsc 0 3 asynreqresource35 rsc 0 2 asynreqresource34 rsc 0 1 asynreqresource33 rsc 0 0 asynreqresource32 rsc 0
108 108 agere systems inc. fw323 05 data sheet, rev. 2 1394a pci phy/link open host controller interface october 2001 internal registers (continued) register: asynchronous request filter high register type: read/set/clear offset: 100h set register 104h clear register default: 0000 0000h table 95. asynchronous request filter high register description bit field name type description 31 asynreqallbuses rsc if this bit is set, then all asynchronous requests received by the fw323 from nonlocal bus nodes are accepted. 30 asynreqresource62 rsc if this bit is set, then asynchronous requests received from node 62 on local bus are accepted by fw323. 29 asynreqresource61 rsc if this bit is set, then asynchronous requests received from node 61 on local bus are accepted by fw323. 28 asynreqresource60 rsc if this bit is set, then asynchronous requests received from node 60 on local bus are accepted by fw323. 27 asynreqresource59 rsc if this bit is set, then asynchronous requests received from node 59 on local bus are accepted by fw323. 26 asynreqresource58 rsc if this bit is set, then asynchronous requests received from node 58 on local bus are accepted by fw323. 25 asynreqresource57 rsc if this bit is set, then asynchronous requests received from node 57 on local bus are accepted by fw323. 24 asynreqresource56 rsc if this bit is set, then asynchronous requests received from node 56 on local bus are accepted by fw323. 23 asynreqresource55 rsc if this bit is set, then asynchronous requests received from node 55 on local bus are accepted by fw323. 22 asynreqresource54 rsc if this bit is set, then asynchronous requests received from node 54 on local bus are accepted by fw323. 21 asynreqresource53 rsc if this bit is set, then asynchronous requests received from node 53 on local bus are accepted by fw323. 20 asynreqresource52 rsc if this bit is set, then asynchronous requests received from node 52 on local bus are accepted by fw323. 19 asynreqresource51 rsc if this bit is set, then asynchronous requests received from node 51 on local bus are accepted by fw323. 18 asynreqresource50 rsc if this bit is set, then asynchronous requests received from node 50 on local bus are accepted by fw323. 17 asynreqresource49 rsc if this bit is set, then asynchronous requests received from node 49 on local bus are accepted by fw323. 16 asynreqresource48 rsc if this bit is set, then asynchronous requests received from node 48 on local bus are accepted by fw323. 15 asynreqresource47 rsc if this bit is set, then asynchronous requests received from node 47 on local bus are accepted by fw323. 14 asynreqresource46 rsc if this bit is set, then asynchronous requests received from node 46 on local bus are accepted by fw323. 13 asynreqresource45 rsc if this bit is set, then asynchronous requests received from node 45 on local bus are accepted by fw323.
agere systems inc. 109 data sheet, rev. 2 fw323 05 october 2001 1394a pci phy/link open host controller interface internal registers (continued) table 95. asynchronous request filter high register description (continued) bit field name type description 12 asynreqresource44 rsc if this bit is set, then asynchronous requests received from node 44 on local bus are accepted by fw323. 11 asynreqresource43 rsc if this bit is set, then asynchronous requests received from node 43 on local bus are accepted by fw323. 10 asynreqresource42 rsc if this bit is set, then asynchronous requests received from node 42 on local bus are accepted by fw323. 9 asynreqresource41 rsc if this bit is set, then asynchronous requests received from node 41 on local bus are accepted by fw323. 8 asynreqresource40 rsc if this bit is set, then asynchronous requests received from node 40 on local bus are accepted by fw323. 7 asynreqresource39 rsc if this bit is set, then asynchronous requests received from node 39 on local bus are accepted by fw323. 6 asynreqresource38 rsc if this bit is set, then asynchronous requests received from node 38 on local bus are accepted by fw323. 5 asynreqresource37 rsc if this bit is set, then asynchronous requests received from node 37 on local bus are accepted by fw323. 4 asynreqresource36 rsc if this bit is set, then asynchronous requests received from node 36 on local bus are accepted by fw323. 3 asynreqresource35 rsc if this bit is set, then asynchronous requests received from node 35 on local bus are accepted by fw323. 2 asynreqresource34 rsc if this bit is set, then asynchronous requests received from node 34 on local bus are accepted by fw323. 1 asynreqresource33 rsc if this bit is set, then asynchronous requests received from node 33 on local bus are accepted by fw323. 0 asynreqresource32 rsc if this bit is set, then asynchronous requests received from node 32 on local bus are accepted by fw323.
110 110 agere systems inc. fw323 05 data sheet, rev. 2 1394a pci phy/link open host controller interface october 2001 internal registers (continued) asynchronous request filter low register the asynchronous request filter low set/clear register is used to enable asynchronous receive requests on a per- node basis, and handles the lower node ids. other than filtering different node ids, this register behaves identically to the asynchronous request filter high register. table 96. asynchronous request filter low register register: asynchronous request filter low register type: read/set/clear offset: 108h set register 10ch clear register default: 0000 0000h bit field name type default 31 asynreqresource31 rsc 0 30 asynreqresource30 rsc 0 29 asynreqresource29 rsc 0 28 asynreqresource28 rsc 0 27 asynreqresource27 rsc 0 26 asynreqresource26 rsc 0 25 asynreqresource25 rsc 0 24 asynreqresource24 rsc 0 23 asynreqresource23 rsc 0 22 asynreqresource22 rsc 0 21 asynreqresource21 rsc 0 20 asynreqresource20 rsc 0 19 asynreqresource19 rsc 0 18 asynreqresource18 rsc 0 17 asynreqresource17 rsc 0 16 asynreqresource16 rsc 0 15 asynreqresource15 rsc 0 14 asynreqresource14 rsc 0 13 asynreqresource13 rsc 0 12 asynreqresource12 rsc 0 11 asynreqresource11 rsc 0 10 asynreqresource10 rsc 0 9 asynreqresource9 rsc 0 8 asynreqresource8 rsc 0 7 asynreqresource7 rsc 0 6 asynreqresource6 rsc 0 5 asynreqresource5 rsc 0 4 asynreqresource4 rsc 0 3 asynreqresource3 rsc 0 2 asynreqresource2 rsc 0 1 asynreqresource1 rsc 0 0 asynreqresource0 rsc 0
agere systems inc. 111 data sheet, rev. 2 fw323 05 october 2001 1394a pci phy/link open host controller interface internal registers (continued) table 97. asynchronous request filter low register description bit field name type description 31 asynreqresource31 rsc if this bit is set for local bus node number 31, then asynchronous requests received by the fw323 from that node are accepted. 30 asynreqresource30 rsc if this bit is set for local bus node number 30, then asynchronous requests received by the fw323 from that node are accepted. 29 asynreqresource29 rsc if this bit is set for local bus node number 29, then asynchronous requests received by the fw323 from that node are accepted. 28 asynreqresource28 rsc if this bit is set for local bus node number 28, then asynchronous requests received by the fw323 from that node are accepted. 27 asynreqresource27 rsc if this bit is set for local bus node number 27, then asynchronous requests received by the fw323 from that node are accepted. 26 asynreqresource26 rsc if this bit is set for local bus node number 26, then asynchronous requests received by the fw323 from that node are accepted. 25 asynreqresource25 rsc if this bit is set for local bus node number 25, then asynchronous requests received by the fw323 from that node are accepted. 24 asynreqresource24 rsc if this bit is set for local bus node number 24, then asynchronous requests received by the fw323 from that node are accepted. 23 asynreqresource23 rsc if this bit is set for local bus node number 23, then asynchronous requests received by the fw323 from that node are accepted. 22 asynreqresource22 rsc if this bit is set for local bus node number 22, then asynchronous requests received by the fw323 from that node are accepted. 21 asynreqresource21 rsc if this bit is set for local bus node number 21, then asynchronous requests received by the fw323 from that node are accepted. 20 asynreqresource20 rsc if this bit is set for local bus node number 20, then asynchronous requests received by the fw323 from that node are accepted. 19 asynreqresource19 rsc if this bit is set for local bus node number 19, then asynchronous requests received by the fw323 from that node are accepted. 18 asynreqresource18 rsc if this bit is set for local bus node number 18, then asynchronous requests received by the fw323 from that node are accepted. 17 asynreqresource17 rsc if this bit is set for local bus node number 17, then asynchronous requests received by the fw323 from that node are accepted. 16 asynreqresource16 rsc if this bit is set for local bus node number 16, then asynchronous requests received by the fw323 from that node are accepted. 15 asynreqresource15 rsc if this bit is set for local bus node number 15, then asynchronous requests received by the fw323 from that node are accepted. 14 asynreqresource14 rsc if this bit is set for local bus node number 14, then asynchronous requests received by the fw323 from that node are accepted. 13 asynreqresource13 rsc if this bit is set for local bus node number 13, then asynchronous requests received by the fw323 from that node are accepted. 12 asynreqresource12 rsc if this bit is set for local bus node number 12, then asynchronous requests received by the fw323 from that node are accepted. 11 asynreqresource11 rsc if this bit is set for local bus node number 11, then asynchronous requests received by the fw323 from that node are accepted. 10 asynreqresource10 rsc if this bit is set for local bus node number 10, then asynchronous requests received by the fw323 from that node are accepted.
112 112 agere systems inc. fw323 05 data sheet, rev. 2 1394a pci phy/link open host controller interface october 2001 internal registers (continued) table 97. asynchronous request filter low register description (continued) bit field name type description 9 asynreqresource9 rsc if this bit is set for local bus node number 9, then asynchronous requests received by the fw323 from that node are accepted. 8 asynreqresource19 rsc if this bit is set for local bus node number 8, then asynchronous requests received by the fw323 from that node are accepted. 7 asynreqresource18 rsc if this bit is set for local bus node number 7, then asynchronous requests received by the fw323 from that node are accepted. 6 asynreqresource17 rsc if this bit is set for local bus node number 6, then asynchronous requests received by the fw323 from that node are accepted. 5 asynreqresource16 rsc if this bit is set for local bus node number 5, then asynchronous requests received by the fw323 from that node are accepted. 4 asynreqresource15 rsc if this bit is set for local bus node number 4, then asynchronous requests received by the fw323 from that node are accepted. 3 asynreqresource14 rsc if this bit is set for local bus node number 3, then asynchronous requests received by the fw323 from that node are accepted. 2 asynreqresource13 rsc if this bit is set for local bus node number 2, then asynchronous requests received by the fw323 from that node are accepted. 1 asynreqresource12 rsc if this bit is set for local bus node number 1, then asynchronous requests received by the fw323 from that node are accepted. 0 asynreqresource11 rsc if this bit is set for local bus node number 0, then asynchronous requests received by the fw323 from that node are accepted.
agere systems inc. 113 data sheet, rev. 2 fw323 05 october 2001 1394a pci phy/link open host controller interface internal registers (continued) physical request filter high register the physical request filter high set/clear register is used to enable physical receive requests on a per-node basis and handle the upper node ids. when a packet is destined for the physical request context and the node id has been compared against the arrq registers, then the comparison is done again with this register. if the bit corresponding to the node id is not set in this register, then the request is handled by the arrq context instead of the physical request context. table 98. physical request filter high register register: physical request filter high register type: read/set/clear offset: 100h set register 104h clear register default: 0000 0000h bit field name type default 31 physreqallbuses rsc 0 30 physreqresource62 rsc 0 29 physreqresource61 rsc 0 28 physreqresource60 rsc 0 27 physreqresource59 rsc 0 26 physreqresource58 rsc 0 25 physreqresource57 rsc 0 24 physreqresource56 rsc 0 23 physreqresource55 rsc 0 22 physreqresource54 rsc 0 21 physreqresource53 rsc 0 20 physreqresource52 rsc 0 19 physreqresource51 rsc 0 18 physreqresource50 rsc 0 17 physreqresource49 rsc 0 16 physreqresource48 rsc 0 15 physreqresource47 rsc 0 14 physreqresource46 rsc 0 13 physreqresource45 rsc 0 12 physreqresource44 rsc 0 11 physreqresource43 rsc 0 10 physreqresource42 rsc 0 9 physreqresource41 rsc 0 8 physreqresource40 rsc 0 7 physreqresource39 rsc 0 6 physreqresource38 rsc 0 5 physreqresource37 rsc 0 4 physreqresource36 rsc 0 3 physreqresource35 rsc 0 2 physreqresource34 rsc 0 1 physreqresource33 rsc 0 0 physreqresource32 rsc 0
114 114 agere systems inc. fw323 05 data sheet, rev. 2 1394a pci phy/link open host controller interface october 2001 internal registers (continued) table 99. physical request filter high register description bit field name type description 31 physreqallbuses rsc if this bit is set, then all asychronous requests received by the fw323 from nonlocal bus nodes are accepted. 30 physreqresource62 rsc if this bit is set, requests received by the fw323 from local bus node 62 will be handled through the physical request context. 29 physreqresource61 rsc if this bit is set, requests received by the fw323 from local bus node 61 will be handled through the physical request context. 28 physreqresource60 rsc if this bit is set, requests received by the fw323 from local bus node 60 will be handled through the physical request context. 27 physreqresource59 rsc if this bit is set, requests received by the fw323 from local bus node 59 will be handled through the physical request context. 26 physreqresource58 rsc if this bit is set, requests received by the fw323 from local bus node 58 will be handled through the physical request context. 25 physreqresource57 rsc if this bit is set, requests received by the fw323 from local bus node 57 will be handled through the physical request context. 24 physreqresource56 rsc if this bit is set, requests received by the fw323 from local bus node 56 will be handled through the physical request context. 23 physreqresource55 rsc if this bit is set, requests received by the fw323 from local bus node 55 will be handled through the physical request context. 22 physreqresource54 rsc if this bit is set, requests received by the fw323 from local bus node 54 will be handled through the physical request context. 21 physreqresource53 rsc if this bit is set, requests received by the fw323 from local bus node 53 will be handled through the physical request context. 20 physreqresource52 rsc if this bit is set, requests received by the fw323 from local bus node 52 will be handled through the physical request context. 19 physreqresource51 rsc if this bit is set, requests received by the fw323 from local bus node 51 will be handled through the physical request context. 18 physreqresource50 rsc if this bit is set, requests received by the fw323 from local bus node 50 will be handled through the physical request context. 17 physreqresource49 rsc if this bit is set, requests received by the fw323 from local bus node 49 will be handled through the physical request context. 16 physreqresource48 rsc if this bit is set, requests received by the fw323 from local bus node 48 will be handled through the physical request context. 15 physreqresource47 rsc if this bit is set, requests received by the fw323 from local bus node 47 will be handled through the physical request context. 14 physreqresource46 rsc if this bit is set, requests received by the fw323 from local bus node 46 will be handled through the physical request context. 13 physreqresource45 rsc if this bit is set, requests received by the fw323 from local bus node 45 will be handled through the physical request context. 12 physreqresource44 rsc if this bit is set, requests received by the fw323 from local bus node 44 will be handled through the physical request context. 11 physreqresource43 rsc if this bit is set, requests received by the fw323 from local bus node 43 will be handled through the physical request context. 10 physreqresource42 rsc if this bit is set, requests received by the fw323 from local bus node 42 will be handled through the physical request context.
agere systems inc. 115 data sheet, rev. 2 fw323 05 october 2001 1394a pci phy/link open host controller interface internal registers (continued) table 99. physical request filter high register description (continued) bit field name type description 9 physreqresource41 rsc if this bit is set, requests received by the fw323 from local bus node 41 will be handled through the physical request context. 8 physreqresource40 rsc if this bit is set, requests received by the fw323 from local bus node 40 will be handled through the physical request context. 7 physreqresource41 rsc if this bit is set, requests received by the fw323 from local bus node 39 will be handled through the physical request context. 6 physreqresource40 rsc if this bit is set, requests received by the fw323 from local bus node 38 will be handled through the physical request context. 5 physreqresource37 rsc if this bit is set, requests received by the fw323 from local bus node 37 will be handled through the physical request context. 4 physreqresource36 rsc if this bit is set, requests received by the fw323 from local bus node 36 will be handled through the physical request context. 3 physreqresource35 rsc if this bit is set, requests received by the fw323 from local bus node 35 will be handled through the physical request context. 2 physreqresource34 rsc if this bit is set, requests received by the fw323 from local bus node 34 will be handled through the physical request context. 1 physreqresource33 rsc if this bit is set, requests received by the fw323 from local bus node 33 will be handled through the physical request context. 0 physreqresource32 rsc if this bit is set, requests received by the fw323 from local bus node 32 will be handled through the physical request context.
116 116 agere systems inc. fw323 05 data sheet, rev. 2 1394a pci phy/link open host controller interface october 2001 internal registers (continued) physical request filter low register the physical request filter low set/clear register is used to enable physical receive requests on a per-node basis and handle the lower node ids. when a packet is destined for the physical request context and the node id has been compared against the asynchronous request filter registers, then the node id comparison is done again with this register. if the bit corresponding to the node id is not set in this register, then the request is handled by the asynchronous request context instead of the physical request context. table 100. physical request filter low register register: physical request filter low register type: read/set/clear offset: 108h set register 11ch clear register default: 0000 0000h bit field name type default 31 physreqresource31 rsc 0 30 physreqresource30 rsc 0 29 physreqresource29 rsc 0 28 physreqresource28 rsc 0 27 physreqresource27 rsc 0 26 physreqresource26 rsc 0 25 physreqresource25 rsc 0 24 physreqresource24 rsc 0 23 physreqresource23 rsc 0 22 physreqresource22 rsc 0 21 physreqresource21 rsc 0 20 physreqresource20 rsc 0 19 physreqresource19 rsc 0 18 physreqresource18 rsc 0 17 physreqresource17 rsc 0 16 physreqresource16 rsc 0 15 physreqresource15 rsc 0 14 physreqresource14 rsc 0 13 physreqresource13 rsc 0 12 physreqresource12 rsc 0 11 physreqresource11 rsc 0 10 physreqresource10 rsc 0 9 physreqresource9 rsc 0 8 physreqresource8 rsc 0 7 physreqresource7 rsc 0 6 physreqresource6 rsc 0 5 physreqresource5 rsc 0 4 physreqresource4 rsc 0 3 physreqresource3 rsc 0 2 physreqresource2 rsc 0 1 physreqresource1 rsc 0 0 physreqresource0 rsc 0
agere systems inc. 117 data sheet, rev. 2 fw323 05 october 2001 1394a pci phy/link open host controller interface internal registers (continued) table 101. physical request filter low register description bit field name type description 31 physreqresource31 rsc if this bit is set, requests received by the fw323 from local bus node 31 will be handled through the physical request context. 30 physreqresource30 rsc if this bit is set, requests received by the fw323 from local bus node 30 will be handled through the physical request context. 29 physreqresource29 rsc if this bit is set, requests received by the fw323 from local bus node 29 will be handled through the physical request context. 28 physreqresource28 rsc if this bit is set, requests received by the fw323 from local bus node 28 will be handled through the physical request context. 27 physreqresource27 rsc if this bit is set, requests received by the fw323 from local bus node 27 will be handled through the physical request context. 26 physreqresource26 rsc if this bit is set, requests received by the fw323 from local bus node 26 will be handled through the physical request context. 25 physreqresource25 rsc if this bit is set, requests received by the fw323 from local bus node 25 will be handled through the physical request context. 24 physreqresource24 rsc if this bit is set, requests received by the fw323 from local bus node 24 will be handled through the physical request context. 23 physreqresource23 rsc if this bit is set, requests received by the fw323 from local bus node 23 will be handled through the physical request context. 22 physreqresource22 rsc if this bit is set, requests received by the fw323 from local bus node 22 will be handled through the physical request context. 21 physreqresource21 rsc if this bit is set, requests received by the fw323 from local bus node 21 will be handled through the physical request context. 20 physreqresource20 rsc if this bit is set, requests received by the fw323 from local bus node 20 will be handled through the physical request context. 19 physreqresource19 rsc if this bit is set, requests received by the fw323 from local bus node 19 will be handled through the physical request context. 18 physreqresource18 rsc if this bit is set, requests received by the fw323 from local bus node 18 will be handled through the physical request context. 17 physreqresource17 rsc if this bit is set, requests received by the fw323 from local bus node 17 will be handled through the physical request context. 16 physreqresource16 rsc if this bit is set, requests received by the fw323 from local bus node 16 will be handled through the physical request context. 15 physreqresource15 rsc if this bit is set, requests received by the fw323 from local bus node 15 will be handled through the physical request context. 14 physreqresource14 rsc if this bit is set, requests received by the fw323 from local bus node 14 will be handled through the physical request context. 13 physreqresource13 rsc if this bit is set, requests received by the fw323 from local bus node 13 will be handled through the physical request context. 12 physreqresource12 rsc if this bit is set, requests received by the fw323 from local bus node 12 will be handled through the physical request context. 11 physreqresource11 rsc if this bit is set, requests received by the fw323 from local bus node 11 will be handled through the physical request context. 10 physreqresource10 rsc if this bit is set, requests received by the fw323 from local bus node 10 will be handled through the physical request context.
118 118 agere systems inc. fw323 05 data sheet, rev. 2 1394a pci phy/link open host controller interface october 2001 internal registers (continued) table 101. physical request filter low register description (continued) bit field name type description 9 physreqresource9 rsc if this bit is set, requests received by the fw323 from local bus node 9 will be handled through the physical request context. 8 physreqresource8 rsc if this bit is set, requests received by the fw323 from local bus node 8 will be handled through the physical request context. 7 physreqresource7 rsc if this bit is set, requests received by the fw323 from local bus node 7 will be handled through the physical request context. 6 physreqresource6 rsc if this bit is set, requests received by the fw323 from local bus node 6 will be handled through the physical request context. 5 physreqresource5 rsc if this bit is set, requests received by the fw323 from local bus node 5 will be handled through the physical request context. 4 physreqresource4 rsc if this bit is set, requests received by the fw323 from local bus node 4 will be handled through the physical request context. 3 physreqresource3 rsc if this bit is set, requests received by the fw323 from local bus node 3 will be handled through the physical request context. 2 physreqresource2 rsc if this bit is set, requests received by the fw323 from local bus node 2 will be handled through the physical request context. 1 physreqresource1 rsc if this bit is set, requests received by the fw323 from local bus node 1 will be handled through the physical request context. 0 physreqresource0 rsc if this bit is set, requests received by the fw323 from local bus node 0 will be handled through the physical request context.
agere systems inc. 119 data sheet, rev. 2 fw323 05 october 2001 1394a pci phy/link open host controller interface internal registers (continued) asynchronous context control register the asynchronous context control set/clear register controls the state and indicates status of the dma context. table 102. asynchronous context control register bit field name type defa ult 31 reserved r 0 30 r 0 29 r 0 28 r 0 27 r 0 26 r 0 25 r 0 24 r 0 23 r 0 22 r 0 21 r 0 20 r 0 19 r 0 18 r 0 17 r 0 16 r 0 15 run rscu 0 14 reserved r 0 13 r 0 12 wake rsu x 11 dead ru 0 10 active ru 0 9 reserved r 0 8r0 7spdrux 6rux 5rux 4 eventcode ru x 3rux 2rux 1rux 0rux
120 120 agere systems inc. fw323 05 data sheet, rev. 2 1394a pci phy/link open host controller interface october 2001 internal registers (continued) register: asynchronous context control register type: read/set/clear/update offset: 180h set register (atrq) 184h clear register (atrq) 1a0h set register (atrs) 1a4h clear register (atrs) 1c0h set register (arrq) 1c4h clear register (arrq) 1e0h set register (atrs) 1e4h clear register (atrs) default: 0000 x0xxh table 103. asynchronous context control register description bit field name type description 31:16 reserved r reserved. bits 31:16 return 0s when read. 15 run rscu this bit is set by software to enable descriptor processing for the context and cleared by software to stop descriptor processing. the fw323 changes this bit only on a hardware or software reset. 14:13 reserved r reserved. bits 14:13 return 0s when read. 12 wake rsu software sets this bit to cause the fw323 to continue or resume descriptor processing. the fw323 clears this bit on every descriptor fetch. 11 dead ru the fw323 sets this bit when it encounters a fatal error and clears the bit when software resets bit 15 (run). 10 active ru the fw323 sets this bit to 1 when it is processing descriptors. 9:8 reserved r reserved. bits 9:8 return 0s when read. 7:5 spd ru this field indicates the speed at which a packet was received or trans- mitted, and only contains meaningful information for receive contexts. this field is encoded as: 000 = 100 mbits/s. 001 = 200 mbits/s. 010 = 400 mbits/s, and all other values are reserved. 4:0 eventcode ru this field holds the acknowledge sent by the link core for this packet or an internally generated error code if the packet was not transferred successfully.
agere systems inc. 121 data sheet, rev. 2 fw323 05 october 2001 1394a pci phy/link open host controller interface internal registers (continued) asynchronous context command pointer register the asynchronous context command pointer register contains a pointer to the address of the first descriptor block that the fw323 accesses when software enables the context by setting the asynchronous context control register bit 15 (run). table 104. asynchronous context command pointer register bit field name type defa ult 31 descriptoraddress rwu x 30 rwu x 29 rwu x 28 rwu x 27 rwu x 26 rwu x 25 rwu x 24 rwu x 23 rwu x 22 rwu x 21 rwu x 20 rwu x 19 rwu x 18 rwu x 17 rwu x 16 rwu x 15 rwu x 14 rwu x 13 rwu x 12 rwu x 11 rwu x 10 rwu x 9rwux 8rwux 7rwux 6rwux 5rwux 4rwux 3zrwux 2rwux 1rwux 0rwux
122 122 agere systems inc. fw323 05 data sheet, rev. 2 1394a pci phy/link open host controller interface october 2001 internal registers (continued) register: asynchronous context command pointer register type: read/write/update offset: 19ch (atrq) 1ach (atrs) 1cch (atrq) 1ech (atrs) default: xxxx xxxxh table 105. asynchronous context command pointer register description bit field name type description 31:4 descriptoraddress rwu contains the upper 28 bits of the address of a 16-byte aligned descriptor block. 3:0 z rwu indicates the number of contiguous descriptors at the address pointed to by the descriptor address. if z is 0, then it indicates that the descrip- toraddress field (bits 31:4) is not valid.
agere systems inc. 123 data sheet, rev. 2 fw323 05 october 2001 1394a pci phy/link open host controller interface internal registers (continued) isochronous transmit context control register the isochronous transmit context control set/clear register controls options, state, and status for the isochronous transmit dma contexts. the n value in the following register addresses indicates the context number (n = 0:7). table 106. isochronous transmit context control register register: isochronous transmit context control register type: read/set/clear/update offset: 200h + (16 * n) set register 204h + (16 * n) clear register default: xxxx x0xxh bit field name type defa ult 31 cyclematchenable rscu x 30 cyclematch rsc x 29 rsc x 28 rsc x 27 rsc x 26 rsc x 25 rsc x 24 rsc x 23 rsc x 22 rsc x 21 rsc x 20 rsc x 19 rsc x 18 rsc x 17 rsc x 16 rsc x 15 run rsc 0 14 reserved r 0 13 r 0 12 wake rsu x 11 dead ru 0 10 active ru 0 9 reserved r 0 8r0 7spdrux 6rux 5rux 4 event code ru x 3rux 2rux 1rux 0rux
124 124 agere systems inc. fw323 05 data sheet, rev. 2 1394a pci phy/link open host controller interface october 2001 internal registers (continued) table 107. isochronous transmit context control register description bit field name type description 31 cyclematchenable rscu when this bit is set to 1, processing occurs such that the packet described by the contexts first descriptor block is transmitted in the cycle whose number is specified in the cyclematch field (bits 30:16). the cyclematch field (bits 30:16) must match the low-order 2 bits of cycleseconds and the 13-bit cyclecount field in the cycle start packet that is sent or received immediately before isochronous transmission begins. since the isochronous transmit dma controller may work ahead, the processing of the first descriptor block may begin slightly in advance of the actual cycle in which the first packet is transmitted. the effects of this bit, however, are impacted by the values of other bits in this register and are explained in the 1394 open host controller inter- face specification . once the context has become active, hardware clears this bit. 30:16 cyclematch rsc contains a 15-bit value, corresponding to the low-order 2 bits of the bus isochronous cycle timer register cycleseconds field (bits 31: 25) and the cyclecount field (bits 24:12). if bit 31 (cyclematchenable) is set, then this isochronous transmit dma context becomes enabled for transmits when the low-order 2 bits of the bus isochronous cycle timer register cycleseconds field (bits 31:25) and the cyclecount field (bits 24:12) value equal this fields (cyclematch) value. 15 run rsc this bit is set by software to enable descriptor processing for the context and cleared by software to stop descriptor processing. the fw323 changes this bit only on a hardware or software reset. 14:13 reserved r reserved. bits 14:13 return 0s when read. 12 wake rsu software sets this bit to cause the fw323 to continue or resume descriptor processing. the fw323 clears this bit on every descriptor fetch. 11 dead ru the fw323 sets this bit when it encounters a fatal error and clears the bit when software resets bit 15 (run). 10 active ru the fw323 sets this bit to 1 when it is processing descriptors. 9:5 reserved r reserved. bits 9:5 return 0s when read. 4:0 event code ru following an output_last* command, the error code is indicated in this field. possible values are: ack_complete, evt_descriptor_read, evt_data_read, and evt_unknown.
agere systems inc. 125 data sheet, rev. 2 fw323 05 october 2001 1394a pci phy/link open host controller interface internal registers (continued) isochronous transmit context command pointer register the isochronous transmit context command pointer register contains a pointer to the address of the first descriptor block that the fw323 accesses when software enables an isochronous transmit context by setting the isochronous transmit context control register bit 15 (run). the n value in the following register addresses indicates the context number (n = 0:7). table 108. isochronous transmit context command pointer register register: isochronous transmit context command pointer register type: read only offset: 20ch + (16 * n) default: xxxx xxxxh bit field name type defa ult 31 descriptoraddress rwu x 30 rwu x 29 rwu x 28 rwu x 27 rwu x 26 rwu x 25 rwu x 24 rwu x 23 rwu x 22 rwu x 21 rwu x 20 rwu x 19 rwu x 18 rwu x 17 rwu x 16 rwu x 15 rwu x 14 rwu x 13 rwu x 12 rwu x 11 rwu x 10 rwu x 9rwux 8rwux 7rwux 6rwux 5rwux 4rwux 3rwux 2rwux 1rwux 0rwux
126 126 agere systems inc. fw323 05 data sheet, rev. 2 1394a pci phy/link open host controller interface october 2001 internal registers (continued) table 109. isochronous transmit context command pointer register description bit field name type description 31:0 descriptoraddress r address of the context program which will be executed when a dma context is started.
agere systems inc. 127 data sheet, rev. 2 fw323 05 october 2001 1394a pci phy/link open host controller interface internal registers (continued) isochronous receive context control register the isochronous receive context control set/clear register controls options, state, and status for the isochronous receive dma contexts. the n value in the following register addresses indicates the context number (n = 0:7). table 110. isochronous receive context control register register: isochronous receive context control register type: read/set/clear/update offset: 400h + (32 * n) set register 404h + (32 *n) clear register default: x000 x0xxh bit field name type defa ult 31 bufferfill rsc x 30 isochheader rsc x 29 cyclematchenable rscu x 28 multichanmode rsc x 27 reserved r x 26 r x 25 r x 24 r x 23 r x 22 r x 21 r x 20 r x 19 r x 18 r x 17 r x 16 r x 15 run rscu x 14 reserved r x 13 r x 12 wake rsu x 11 dead ru x 10 active ru x 9 reserved r x 8rx 7spdrux 6rux 5rux 4 event code ru x 3rux 2rux 1rux 0rux
128 128 agere systems inc. fw323 05 data sheet, rev. 2 1394a pci phy/link open host controller interface october 2001 internal registers (continued) table 111. isochronous receive context control register description bit field name type description 31 bufferfill rsc when this bit is set, received packets are placed back-to-back to com- pletely fill each receive buffer. when this bit is cleared, each received packet is placed in a single buffer. if bit 28 (multichanmode) is set to 1, then this bit must also be set to 1. the value of this bit must not be changed while bit 10 (active) or bit 15 (run) is set. 30 isochheader rsc when this bit is 1, received isochronous packets include the complete 4-byte isochronous packet header seen by the link layer. the end of the packet is marked with an xferstatus in the first doublet, and a 16-bit timestamp indicating the time of the most recently received (or sent) cyclestart packet. when this bit is cleared, the packet header is stripped off of received isochronous packets. the packet header, if received, immediately precedes the packet payload. the value of this bit must not be changed while bit 10 (active) or bit 15 (run) is set. 29 cyclematchenable rscu when this bit is set, the context begins running only when the 13-bit cyclematch field (bits 24:12) in the isochronous receive context match register matches the 13-bit cyclecount field in the cyclestart packet. the effects of this bit, however, are impacted by the values of other bits in this register. once the context has become active, hardware clears this bit. the value of this bit must not be changed while bit 10 (active) or bit 15 (run) is set. 28 multichanmode rsc when this bit is set, the corresponding isochronous receive dma context receives packets for all isochronous channels enabled in the isochro- nous receive channel mask high and isochronous receive channel mask low registers. the isochronous channel number specified in the isochro- nous receive dma context match register is ignored. when this bit is cleared, the isochronous receive dma context receives packets for the channel number specified in the context match register. only one isoch- ronous receive dma context may use the isochronous receive channel mask registers. if more that one isochronous receive context control reg- ister has this bit set, then results are undefined. the value of this bit must not be changed while bit 10 (active) or bit 15 (run) is set to 1. 27:16 reserved r reserved. bits 27:16 return 0s when read. 15 run rscu this bit is set by software to enable descriptor processing for the context and cleared by software to stop descriptor processing. the fw323 changes this bit only on a hardware or software reset. 14:13 reserved r reserved. bits 14:13 return 0s when read. 12 wake rsu software sets this bit to cause the fw323 to continue or resume descrip- tor processing. the fw323 clears this bit on every descriptor fetch. 11 dead ru the fw323 sets this bit when it encounters a fatal error and clears the bit when software resets bit 15 (run). 10 active ru the fw323 sets this bit to 1 when it is processing descriptors. 9:8 reserved r reserved. bits 9:8 return 0s when read. 7:5 spd ru this field indicates the speed at which the packet was received. 000 = 100 mbits/s. 001 = 200 mbits/s. 010 = 400 mbits/s. all other values are reserved. 4:0 event code ru following an input_* command, the error or status code is indicated in this field.
agere systems inc. 129 data sheet, rev. 2 fw323 05 october 2001 1394a pci phy/link open host controller interface internal registers (continued) isochronous receive context command pointer register the isochronous receive context command pointer register contains a pointer to the address of the first descriptor block that the fw323 accesses when software enables an isochronous receive context by setting the isochronous receive context control register bit 15 (run). the n value in the following register addresses indicates the context number (n = 0:7). table 112. isochronous receive context command pointer register register: isochronous receive context command pointer register type: read only offset: 40ch + (32 * n) default: xxxx xxxxh bit field name type defa ult 31 descriptoraddress rwu x 30 rwu x 29 rwu x 28 rwu x 27 rwu x 26 rwu x 25 rwu x 24 rwu x 23 rwu x 22 rwu x 21 rwu x 20 rwu x 19 rwu x 18 rwu x 17 rwu x 16 rwu x 15 rwu x 14 rwu x 13 rwu x 12 rwu x 11 rwu x 10 rwu x 9rwux 8rwux 7rwux 6rwux 5rwux 4rwux 3rwux 2rwux 1rwux 0rwux
130 130 agere systems inc. fw323 05 data sheet, rev. 2 1394a pci phy/link open host controller interface october 2001 internal registers (continued) table 113. isochronous receive context command pointer register description bit field name type description 31:0 descriptoraddress rwu address of the context program which will be executed when a dma context is started.
agere systems inc. 131 data sheet, rev. 2 fw323 05 october 2001 1394a pci phy/link open host controller interface internal registers (continued) isochronous receive context match register the isochronous receive context match register is used to control on which isochronous cycle the context should start. the register is also used to control which packets are accepted by the context. table 114. isochronous receive context match register register: isochronous receive context match register type: read only offset: 410ch + (32 * n) default: xxxx xxxxh bit field name type defa ult 31 tag3 rw x 30 tag2 rw x 29 tag1 rw x 28 tag0 rw x 27 reserved r 0 26 r 0 25 r 0 24 cyclematch rw x 23 rw x 22 rw x 21 rw x 20 rw x 19 rw x 18 rw x 17 rw x 16 rw x 15 rw x 14 rw x 13 rw x 12 rw x 11 sync rw x 10 rw x 9rwx 8rwx 7 reserved r x 6 tag1syncfilter rw x 5 channelnumber rw x 4rwx 3rwx 2rwx 1rwx 0rwx
132 132 agere systems inc. fw323 05 data sheet, rev. 2 1394a pci phy/link open host controller interface october 2001 internal registers (continued) table 115. isochronous receive context match register description bit field name type description 31 tag3 rw if this bit is set, then this context matches on iso receive packets with a tag field of 11b. 30 tag2 rw if this bit is set, then this context matches on iso receive packets with a tag field of 10b. 29 tag1 rw if this bit is set, then this context matches on iso receive packets with a tag field of 01b. 28 tag0 rw if this bit is set, then this context matches on iso receive packets with a tag field of 00b. 27:25 reserved r reserved. bits 27:25 return 0s when read. 24:12 cyclematch rw contains a 15-bit value, corresponding to the low-order 2 bits of cycle- seconds and the 13-bit cyclecount field in the cyclestart packet. if iso- chronous receive context control register bit 29 (cyclematchenable) is set, then this context is enabled for receives when the 2 low-order bits of the bus isochronous cycle timer register cycleseconds field (bits 31:25) and cyclecount field (bits 24:12) value equal this fields (cyclem- atch) value. 11:8 sync rw this field contains the 4-bit field which is compared to the sync field of each iso packet for this channel when the command descriptors w field is set to 11b. 7 reserved r reserved. bit 7 returns 0 when read. 6 tag1syncfilter rw if this bit and bit 29 (tag1) are set, then packets with tag2b01 are accepted into the context if the two most significant bits of the packets sync field are 00b. packets with tag values other than 01b are filtered according to tag0, tag2, and tag3 (bits 28, 30, and 31, respectively) without any additional restrictions. if this bit is cleared, then this context matches on isochronous receive packets as specified in bits 28:31 (tag0:tag3) with no additional restrictions. 5:0 channelnumber rw this 6-bit field indicates the isochronous channel number for which this isochronous receive dma context accepts packets.
agere systems inc. 133 data sheet, rev. 2 fw323 05 october 2001 1394a pci phy/link open host controller interface internal registers (continued) fw323 vendor specific registers the fw323 contains a number of vendor-defined registers used for diagnostics and control low-level hardware functions. these registers are addressable in the upper 2k of the 4k region defined by pci base address register 0 (registers defined by the ohci specification reside in the lower 2k of this region). the control registers should not be changed when the link is enabled. table 116. fw323 vendor specific registers description offset register name description 12h800 isodmactrl controls pci access for the isochronous dma contents. initial values are loaded from serial eeprom, if present. 12h808 asydmactrl controls pci access and at fifo threshold for the asynchronous dma contexts. initial values are loaded from serial eeprom, if present. 12h840 linkoptions controls low level functionality of the link core. initial values are loaded from serial eeprom, if present.
134 134 agere systems inc. fw323 05 data sheet, rev. 2 1394a pci phy/link open host controller interface october 2001 internal registers (continued) isochronous dma control the fields in this register control when the isochronous dma engines access the pci bus and how much data they will attempt to move in a single pci transaction. the actual pci burst sizes will also be affected by 1394 packet size, host memory buffer size, fifo constraints, and the pci cache line size. this register is accessible via the pci bus at offset 0x800. table 117. isochronous dma control registers description bits field description 15:12 it maximum burst the maximum number of quadlets that will be fetched by the it unit in one pci transaction. the maximum burst is 16 * (n + 1) quadlets. defaults to 7 (128 quadlets). 11:8 it threshold along with the amount of data remaining to be fetched from the current host memory buffer, this field defines the number of quadlets that must be unused in the it fifo before the it unit will request access to the pci bus. in effect, this value defines the minimum burst size that, other factors permitting, will be used in it. the threshold is 16 * (n + 1) quadlets and defaults to 3 (64 quadlets). 7:4 ir maximum burst the maximum number of quadlets that will be written by the ir unit in one pci transaction. the maximum burst is 16 * (n + 1) quadlets. defaults to 7 (128 quadlets). 3:0 ir threshold along with the space remaining in the current host memory buffer, this field defines the number of quadlets that must be available in the ir fifo before the ir unit will request access to the pci bus. the threshold is 16 * (n + 1) quadlets and defaults to 3 (64 quadlets).
agere systems inc. 135 data sheet, rev. 2 fw323 05 october 2001 1394a pci phy/link open host controller interface internal registers (continued) asynchronous dma control this register is accessible via the pci bus at offset 0x808. table 118. asynchronous dma control registers description bits field description 23:16 at fifo threshold the number of quadlets of a packet that must be in the at fifo before the link will be notified that there is an asynchronous packet to be trans- mitted. (the link will also be signaled that a packet is available for trans- mission if the entire packet is in the fifo, regardless of its size.) defaults to a value of 0x10 (256 quadlets). 15:12 at maximum burst the maximum number of quadlets that will be fetched by the at and physical read response units in one pci transaction. the maximum burst is 16 * (n + 1) quadlets. defaults to 7 (128 quadlets). 11:8 at threshold along with the amount of data remaining to be fetched from the current host memory buffer, this field defines the number of quadlets that can be written to the at fifo before the at and physical read response units will request access to the pci bus. the threshold is 16 * (n + 1) quadlets and defaults to 3 (64 quadlets). 7:4 ar maximum burst the maximum number of quadlets that will be written by the ar and physical write units in one pci transaction. the maximum burst is 16 * (n + 1) quadlets. defaults to 7 (128 quadlets). 3:0 ar threshold along with the space remaining in the current host memory buffer, this field defines the number of quadlets that must be available in the ar fifo before the ar unit will request access to the pci bus. for the physical write unit, this value defines the minimum pci burst, packet size permitting. the threshold is 16 * (n + 1) quadlets and defaults to 3 (64 quadlets).
136 136 agere systems inc. fw323 05 data sheet, rev. 2 1394a pci phy/link open host controller interface october 2001 internal registers (continued) link options the values in this register control the operation of the link module within the fw323 beyond what is stated in 1394 and ohci specifications. in general, these controls are to be used for debugging and diagnostic purposes only and should not be modified from power reset default values. this register is accessible via the pci bus at offset 0x840. table 119. link registers description bits field description 5:3 posted wires number of physical posted writes the link is allowed to queue in the asynchro- nous receive fifo. defaults to four, which is the maximum value. values greater than four will disable all physical posted writes. 2:0 cycle timer control selects the value the fw323 will use for its isochronous cycle period when the fw323 is the root node. this value is for debugging purposes only and should not be set to other than its default value in a real 1394 network. this value defaults to 0. if 0, cycle = 125 m s. if 1, cycle = 62.5 m s. if 2, cycle = 31.25 m s. if 3, cycle = 15.625 m s. if 4, cycle = 7.8125 m s.
agere systems inc. 137 data sheet, rev. 2 fw323 05 october 2001 1394a pci phy/link open host controller interface internal registers (continued) table 120. rom format description byte address description 0x00 subsystem vendor id, 1 s byte 0x01 subsystem vendor id, ms byte 0x02 subsystem id, 1 s byte 0x03 subsystem id, ms byte 0x04 pci min grant value 0x05 pci max latency value 0x06 reserved 0x07 pci global swap control (bit 0) 0x08 isodmactrl[7:0] 0x09 isodmactrl[15:8] 0x0a isodmactrl[23:16] 0x0b isodmactrl[31:24] 0x0c asydmactrl[7:0] 0x0d asydmactrl[15:8] 0x0e asydmactrl[23:16] 0x0f asydmactrl[31:24] 0x10 linkoptions[7:0] 0x11 linkoptions[15:8] 0x12 linkoptions[23:16] 0x13 linkoptions[31:24] 0x14 ohci bus options[7:0] 0x15 ohci bus options[15:8] 0x16 ohci bus options[23:16] 0x17 ohci bus options[31:24] 0x18 ohci guidhi[7:0] 0x19 ohci guidhi[15:8] 0x1a ohci guidhi[23:16] 0x1b ohci guidhi[31:24] 0x1c ohci guidlo[7:0] 0x1d ohci guidlo[15:8] 0x1e ohci guidlo[23:16] 0x1f ohci guidlo[31:24] 0x20 ohci configromhdr[7:0] 0x21 ohci configromhdr[15:8] 0x22 ohci configromhdr[23:16] 0x23 ohci configromhdr[31:24] 0x24 start of system defined configuration space
138 138 agere systems inc. fw323 05 data sheet, rev. 2 1394a pci phy/link open host controller interface october 2001 crystal selection considerations the fw323 is designed to use an external 24.576 mhz crystal connected between the xi and xo terminals to pro- vide the reference for an internal oscillator circuit. ieee 1394a-2000 standard requires that fw323 have less than 100 ppm total variation from the nominal data rate, which is directly influenced by the crystal. to achieve this, it is recommended that an oscillator with a nominal 50 ppm or less frequency tolerance be used. the total frequency variation must be kept below 100 ppm from nominal with some allowance for error introduced by board and device variations. trade-offs between frequency tolerance and stability may be made as long as the total frequency variation is less than 100 ppm. load capacitance the frequency of oscillation is dependent upon the load capacitance specified for the crystal, in parallel resonant mode crystal circuits. total load capacitance (c l ) is a function of not only the discrete load capacitors, but also capacitances from the fw323 board traces and capacitances of the other fw323 connected components.the val- ues for load capacitors (c a and c b ) should be calculated using this formula: c a =c b =(c l Cc stray ) 2 where: c l = load capacitance specified by the crystal manufacturer c stray = capacitance of the board and the fw323, typically 2 pf3 pf board layout the layout of the crystal portion of the phy circuit is important for obtaining the correct frequency and minimizing noise introduced into the fw323 pll. the crystal and two-load capacitors should be considered as a unit during layout. they should be placed as close as possible to one another, while minimizing the loop area created by the combination of the three components. minimizing the loop area minimizes the effect of the resonant current that flows in this resonant circuit. this layout unit (crystal and load capacitors) should then be placed as close as possi- ble to the phy xi and xo terminals to minimize trace lengths. vias should not be used to route the x1 and x0 sig- nals. absolute maximum ratings stresses in excess of the absolute maximum ratings can cause permanent damage to the device. these are abso- lute stress ratings only. functional operation of the device is not implied at these or any other conditions in excess of those given in the operational sections of the data sheet. exposure to absolute maximum ratings for extended periods can adversely affect device reliability. table 121. absolute maximum ratings * except for 5 v tolerant i/o (ctl0, ctl1, d0d7, and lreq), where v i max = 5.5 v. parameter symbol min max unit supply voltage range v dd 3.0 3.6 v input voltage range* v i - 0.5 v dd +0.5 v output voltage range at any output v o - 0.5 v dd +0.5 v operating free air temperature t a 070 c storage temperature range t stg C65 150 c
agere systems inc. 139 data sheet, rev. 2 fw323 05 october 2001 1394a pci phy/link open host controller interface electrical characteristics table 122. analog characteristics parameter test conditions symbol min typ max unit supply voltage source power node v ddsp 3.0 3.3 3.6 v differential input voltage cable inputs, 100 mbits/s operation v id100 142 260 mv cable inputs, 200 mbits/s operation v id200 132 260 mv cable inputs, 400 mbits/s operation v id400 100 260 mv cable inputs, during arbitration v idarb 168 265 mv common-mode voltage source power mode tpb cable inputs, speed signaling off v cm 1.165 2.515 v tpb cable inputs, s100 speed signaling on v cmsp100 1.165 2.515 v tpb cable inputs, s200 speed signaling on v cmsp200 0.935 2.515 v tpb cable inputs, s400 speed signaling on v cmsp400 0.532 2.515 v common-mode voltage nonsource power mode* * for a node that does not source power (see section 4.2.2.2 in ieee 1394-1995 standard). tpb cable inputs, speed signaling off v cm 1.165 2.015 v tpb cable inputs, s100 speed signaling on v cmnsp100 1.165 2.015 v tpb cable inputs, s200 speed signaling on v cmnsp200 0.935 2.015 v tpb cable inputs, s400 speed signaling on v cmnsp400 0.532 2.015 v receive input jitter tpa, tpb cable inputs, 100 mbits/s operation 1.08ns tpa, tpb cable inputs, 200 mbits/s operation 0.5ns tpa, tpb cable inputs, 400 mbits/s operation 0.315 ns receive input skew between tpa and tpb cable inputs, 100 mbits/s operation 0.8ns between tpa and tpb cable inputs, 200 mbits/s operation 0.55ns between tpa and tpb cable inputs, 400 mbits/s operation 0.5ns positive arbitration comparator input threshold voltage v th + 89 168 mv negative arbitration comparator input threshold voltage v th - C168 C89 mv speed signal input threshold voltage 200 mbits/s v ths200 45 139 mv 400 mbits/s v ths400 266 445 mv output current tpbias outputs i o C5 2.5 ma tpbias output voltage at rated i/o current v o 1.665 2.015 v current source for connect detect circuit i cd 76 m a
140 140 agere systems inc. fw323 05 data sheet, rev. 2 1394a pci phy/link open host controller interface october 2001 electrical characteristics (continued) table 123. driver characteristics table 124. device characteristics parameter test conditions symbol min typ max unit differential output voltage 56 w load v od 172 265 mv off-state common-mode voltage drivers disabled v off 20mv driver differential current, tpa+, tpa - , tpb+, tpb - driver enabled, speedsignalingoff* * limits are defined as the algebraic sum of tpa+ and tpa - driver currents. limits also apply to tpb+ and tpb - as the algebraic sum of driver currents. ? limits are defined as the absolute limit of each of tpb+ and tpb - driver currents. i diff - 1.05 1.05 ma common-mode speed signaling current, tpb+, tpb - 200 mbits/s speed signaling enabled ? i sp - 2.53 - 4.84 ma 400 mbits/s speed signaling enabled ? i sp - 8.1 - 12.4 ma parameter test conditions symbol min typ max unit supply current: d0, 3 ports active cyclestartsonbus d0, 2 ports active cyclestartsonbus d0, 1 port active cyclestartsonbus d1, lps on, link ready, 1 port active, pci clock off (or very slow) wake-up is possible from this state d2, lps off, pci clock off (or slow), ports suspended, phy core off, wake-up is possible from this state d3hot, lps off, pci clock off (or slow), ports disabled, phy core off, wake-up is possible from this state d3cold, power is removed from chip, no wake-up is possible from this state v dd =3.3v i dd 158 140 122 86 <1 <1 0 ma ma ma ma ma ma ma high-level output voltage i oh max, v dd =min v oh v dd C0.4 v low-level output voltage i ol min, v dd =max v ol 0.4v high-level input voltage cmos inputs v ih 0.7v dd v low-level input voltage cmos inputs v il 0.2v dd v pull-up current, resetn input v i =0v i i 11 32 m a
agere systems inc. 141 data sheet, rev. 2 fw323 05 october 2001 1394a pci phy/link open host controller interface timing characteristics table 125. switching characteristics table 126. clock characteristics ac characteristics of serial eeprom interface signals table 127. ac characteristics of serial eeprom interface signals symbol parameter measured test conditions min typ max unit jitter, transmit tpa, tpb 0.15 ns transmit skew between tpa and tpb 0.1 ns t r rise time, transmit (tpa/tpb) 10% to 90% r i =56 w, c i =10pf 1.2ns t f fall time, transmit (tpa/tpb) 90% to 10% r i =56 w, c i =10pf 1.2ns parameter symbol min typ max unit external clock source frequency f 24.5735 24.5760 24.5785 mhz symbol parameter min max units f rom_clk frequency of serial clock 100 khz t pw_low width of serial clock pulse low 4.7 m s t pw_high width of serial clock pulse high 4.0 m s t data_valid time from when serial clock transitions low until eeprom returns valid data 0.1 4.5 m s t free time i2c bus must be idle before a new transaction can be started 4.7 m s t hold_start fw323 hold time for a valid start condition 4.0 m s t setup_start fw323 setup time for a valid start condition 4.7 m s t hold_data data out hold time for the fw323 0 m s t setup_data data out setup time for the fw323 200 ns t rise_time rise time for serial clock and data out from the fw323 1.0 m s t fall_time fall time for serial clock and data out from the fw323 300 ns t setup_stop fw323 setup time for a valid stop condition 4.7 m s t hold_eeprom data out hold time for eeprom 100 ns
142 142 agere systems inc. fw323 05 data sheet, rev. 2 1394a pci phy/link open host controller interface october 2001 ac characteristics (continued) rom_clk: serial clock, rom_ad: serial data i/o 1313 (f) r.02 figure 5. bus timing rom_clk: serial clock, rom_ad: serial data i/o 1314 (f) r.02 figure 6. write cycle timing rom_clk: serial clock, rom_ad: serial data i/o 1310 (f) r.02 figure 7. data validity t setup_start t hold_start t fall_time t pw_low t pw_high t rise_time t setup_stop t setup_data t hold_data t free t data_valid rom_clk rom_ad in rom_ad out t hold_eeprom t pw_low rom_clk rom_ad 8th bit ack word n stop start t wr(1) stable stable change rom_ad rom_clk
agere systems inc. 143 data sheet, rev. 2 fw323 05 october 2001 1394a pci phy/link open host controller interface ac characteristics (continued) rom_clk: serial clock, rom_ad: serial data i/o 1311 (f) r.02 figure 8. start and stop definition rom_clk: serial clock 1312 (f) r.02 figure 9. output acknowledge start stop rom_ad rom_clk rom_clk data in data out start ack 189
144 144 agere systems inc. fw323 05 data sheet, rev. 2 1394a pci phy/link open host controller interface october 2001 internal register configuration phy core register map for cable environment the phy core register map is shown below in table 128. table 128. phy core register map for the cable environment address contents bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 0000 2 physical_id r ps 0001 2 rhb ibr gap_count 0010 2 extended (7) xxxxx total_ports 0011 2 max_speed xxxxx delay 0100 2 lctrl contender jitter pwr_class 0101 2 watchdog isbr loop pwr_fail timeout port_event enab_accel enab_multi 0110 2 xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx 0111 2 page_select xxxxx port_select 1000 2 register 0 page_select 1111 2 register 7 page_select required xxxxx reserved
agere systems inc. 145 data sheet, rev. 2 fw323 05 october 2001 1394a pci phy/link open host controller interface internal register configuration (continued) phy core register fields for cable environment table 129. phy core register fields for cable environment field size type power reset value description physical_id 6 r 000000 the address of this node is determined during self-identification. a value of 63 indicates a malconfigured bus; the link will not transmit any packets. r 1 r 0 when set to one, indicates that this node is the root. ps 1 r cable power active. rhb 1 rw 0 root hold-off bit. when set to one, the force_root variable is true, which instructs the phy core to attempt to become the root during the next tree identify process. ibr 1 rw 0 initiate bus reset. when set to one, instructs the phy core to set ibr true and reset_time to reset_time. these values in turn cause the phy core to initiate a bus reset without arbitration; the reset signal is asserted for 166 m s. this bit is self-clearing. gap_count 6 rw 3f 16 used to configure the arbitration timer setting in order to optimize gap times according to the topology of the bus. see section 4.3.6 of ieee standard 1394-1995 for the encoding of this field. extended 3 r 7 this field has a constant value of seven, which indicates the extended phy core register map. total_ports 4 r 3 the number of ports implemented by this phy core. this count reflects the number. max_speed 3 r 010 2 indicates the speed(s) this phy core supports: 000 2 = 98.304 mbits/s. 001 2 = 98.304 and 196.608 mbits/s. 010 2 = 98.304, 196.608, and 393.216 mbits/s. 011 2 = 98.304, 196.608, 393.216, and 786.43 mbits/s. 100 2 = 98.304, 196.608, 393.216, 786.432, and 1,572.864 mbits/s. 101 2 = 98.304, 196.608, 393.216, 786.432, 1,572.864, and 3,145.728 mbits/s. all other values are reserved for future definition. delay 4 r 0000 worst-case repeater delay, expressed as 144 + (delay * 20) ns. lctrl 1 rw 1 link active. cleared or set by software to control the value of the l bit transmitted in the nodes self-id packet 0, which will be the logi- cal and of this bit and lps active. contender 1 rw see description cleared or set by software to control the value of the c bit transmit- ted in the self-id packet. powerup reset value is set by contender pin. jitter 3 r 000 the difference between the fastest and slowest repeater data delay, expressed as (jitter + 1) * 20 ns. pwr_class 3 rw see description power-class. controls the value of the pwr field transmitted in the self-id packet. see section 4.3.4.1 of ieee standard 1394-1995 for the encoding of this field. pc0, pc1, and pc2 pins set up power reset value.
146 146 agere systems inc. fw323 05 data sheet, rev. 2 1394a pci phy/link open host controller interface october 2001 internal register configuration (continued) table 129. phy core register fields for cable environment (continued) field size type power reset value description watchdog 1 rw 0 when set to one, the phy core will set port_event to one if resume operations commence for any port. isbr 1 rw 0 initiate short (arbitrated) bus reset. a write of one to this bit instructs the phy core to set isbr true and reset_time to short_reset_time. these values in turn cause the phy core to arbitrate and issue a short bus reset. this bit is self- clearing. loop 1 rw 0 loop detect. a write of one to this bit clears it to zero. pwr_fail 1 rw 1 cable power failure detect. set to one when the ps bit changes from one to zero. a write of one to this bit clears it to zero. timeout 1 rw 0 arbitration state machine timeout. a write of one to this bit clears it to zero (see max_arb_state_time). port_event 1 rw 0 port event detect. the phy core sets this bit to one if any of connected, bias, disabled, or fault change for a port whose int_enable bit is one. the phy core also sets this bit to one if resume operations commence for any port and watchdog is one. a write of one to this bit clears it to zero. enab_accel 1 rw 0 enable arbitration acceleration. when set to one, the phy core will use the enhancements specified in clause 7.10 of 1394a-2000 specification. phy core behavior is unspecified if the value of enab_accel is changed while a bus request is pending. enab_multi 1 rw 0 enable multispeed packet concatenation. when set to one, the link will signal the speed of all packets to the phy core. page_select 3 rw 000 selects which of eight possible phy core register pages are accessible through the window at phy core register addresses 1000 2 through 1111 2 , inclusive. port_select 4 rw 0000 if the page selected by page_select presents per-port informa- tion, this field selects which ports registers are accessible through the window at phy core register addresses 1000 2 through 1111 2 , inclusive. ports are numbered monotonically starting at zero, p0.
agere systems inc. 147 data sheet, rev. 2 fw323 05 october 2001 1394a pci phy/link open host controller interface internal register configuration (continued) the port status page is used to access configuration and status information for each of the phy cores ports. the port is selected by writing zero to page_select and the desired port number to port_select in the phy core register at address 0111 2 . the format of the port status page is illustrated by table 130 below; reserved fields are shown as xxxxx. the m eanings of the register fields with the port status page are defined by rsc. table 130. phy core register page 0: port status page address contents bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 1000 2 astat bstat child connected bias disabled 1001 2 negotiated_speed int_enable fault xxxxx xxxxx xxxxx 1010 2 xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx 1011 2 xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx 1100 2 xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx 1101 2 xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx 1110 2 xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx 1111 2 xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx required xxxxx reserved
148 agere systems inc. fw323 05 data sheet, rev. 2 1394a pci phy/link open host controller interface october 2001 internal register configuration (continued) the meaning of the register fields with the port status page are defined by table 131 below. table 131. phy core register port status page fields field size type power reset value description astat 2 r tpa line state for the port: 00 2 = invalid. 01 2 =1. 10 2 =0. 11 2 =z. bstat 2 r tpb line state for the port (same encoding as astat). child 1 r 0 if equal to one, the port is a child; otherwise, a parent. the meaning of this bit is undefined from the time a bus reset is detected until the phy core transitions to state t1: child handshake during the tree identify process (see section 4.4.2.2 in ieee standard 1394-1995). connected 1 r 0 if equal to one, the port is connected. bias 1 r 0 if equal to one, incoming tpbias is detected. disabled 1 rw 0 if equal to one, the port is disabled. negotiated_speed 3 r 000 indicates the maximum speed negotiated between this phy core port and its immediately connected port; the encoding is the same as for they phy core register max_speed field. int_enable 1 rw 0 enable port event interrupts. when set to one, the phy core will set port_event to one if any of connected, bias, disabled, or fault (for this port) change state. fault 1 rw 0 set to one if an error is detected during a suspend or resume operation. a write of one to this bit clears it to zero.
agere systems inc. 149 data sheet, rev. 2 fw323 05 october 2001 1394a pci phy/link open host controller interface internal register configuration (continued) the vendor identification page is used to identify the phy cores vendor and compliance level. the page is selected by writing one to page_select in the phy core register at address 0111 2 . the format of the vendor identi- fication page is shown in table 132; reserved fields are shown as xx xxx. table 132. phy core register page 1: vendor identification page note: the meaning of the register fields within the vendor identification page are defined by table 133. table 133. phy core register vendor identification page fields note: the vendor-dependent page provides access to information used in the manufacturing test of the fw323. address contents bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 1000 2 compliance_level 1001 2 xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx 1010 2 1011 2 vendor_id 1100 2 1101 2 1110 2 product_id 1111 2 required xxxxx reserved field size type description compliance_level 8 r standard to which the phy core implementation complies: 0 = not specified 1= ieee 1394a-2000 ageres fw323 compliance level is 1. all other values reserved for future standardization. vendor_id 24 r the company id or organizationally unique identifier (oui) of the manufacturer of the phy core. ageres vendor id is 00601d 16 . this number is obtained from the ieee registration authority committee (rac). the most significant byte of vendor_id appears at phy core register location 1010 2 and the least significant at 1100 2 . product_id 24 r the meaning of this number is determined by the company or organization that has been granted vendor_id. ageres fw323 phy core product id is 032304 16 . the most significant byte of product_id appears at phy core register location 1101 2 and the least significant at 1111 2 .
150 agere systems inc. fw323 05 data sheet, rev. 2 1394a pci phy/link open host controller interface october 2001 outline diagrams 128-pin tqfp dimensions are in millimeters. 5-4427r.2 (f) 0.19/0.27 0.08 m 0.106/0.200 detail b 0.25 0.45/0.75 1.00 ref gage plane seating plane detail a detail a detail b 1.60 max 0.50 typ seating plane 0.08 1.40 0.05 0.05/0.15 1 38 65 102 103 128 pin#1identifierzone 16.00 0.20 14.00 0.20 20.00 0.20 22.00 0.20 64 39
agere systems inc. 151 data sheet, rev. 2 fw323 05 october 2001 1394a pci phy/link open host controller interface notes
agere systems inc. reserves the right to make changes to the product(s) or information contained herein without notice. no liab ility is assumed as a result of their use or application. copyright ? 2001 agere systems inc. all rights reserved october 2001 ds01-124cmpr-2 (replaces ds01-124cmpr-1) for additional information, contact your agere systems account manager or the f ollowing: internet: http://www.agere.com e-mail: docmaster@agere.com n. america: agere systems inc., 555 union bo ulevard, room 30l-15p-ba, allentown, pa 18109-3286 1-800-372-2447 , fax 610-712-4106 (in canada: 1-800-553-2448 , fax 610-712-4106) asia: agere systems hong kong ltd., suites 3201 & 3210-12, 32/f, tower 2, the gateway, harbour city, kowloon tel. (852) 3129-2000 , fax (852) 3129-2020 china: (86) 21-5047-1212 (shanghai), (86) 10-6522-5566 (beijing), (86) 755-695-7224 (shenzhen) japan: (81) 3-5421-1600 (tokyo), korea: (82) 2-767-1850 (seoul), singapore: (65) 778-8833 , taiwan: (886) 2-2725-5858 (taipei) europe: tel. (44) 7000 624624 , fax (44) 1344 488 045 fw323 05 data sheet, rev. 2 1394a pci phy/link open host controller interface october 2001 microsoft and windows are registered trademarks of microsoft corporation. macos is a registered trademark of apple computer, inc. ieee is a registered trademark of the institute of electrical and electronics engineers, inc.

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